Analysis of the conventional LNA

Ⅳ. Implementation of multi-physiological sensing ROIC

4.2 Implementation of biopotential analog front-end

4.2.1 Low-noise amplifier

4.2.1.1 Analysis of the conventional LNA

Figure 4.3(a) shows a schematic of the LNA with capacitive-coupled instrumentation amplifier (CCIA) topology. The ripple reduction loop and the impedance boosting loop which is shown in figure 4.2 are removed to simplify the analysis. Among the main characteristics of the CCIA, the pass-band gain, HPF cutoff frequency, and input DC offset tolerance can be known from the figure 4.3(a). Transfer function of the CCIA is expressed as equation (4.1).

V_OUT

V_IN = −C_IN

C_FB· 1

1 + C_A−DSL sR_INTC_INTC_FB

(4.1)

From the equation (4.1), the pass-band gain (AV) and HPF cutoff frequency (whp)of the CCIA are

28 expressed as follow,

A_V = −C_IN CFB

(4.2) w_hp = C_A−DSL

R_INTC_INTC_FB (4.3)

where the capacitors and resistors are design parameters of the CCIA. In the CCIA design, the appropriate AV is set in consideration of the input signal amplitude and the input-referred noise performance. The design parameters are fixed as CIN = 6pF and CFB = 60fF to obtain the pass-band gain of 40dB. Biopotential signals can be measured normally only when the whp which is related to various design parameters is designed to be lower than the biopotential signal frequency.

On the other hand, input DC offset (IDO) tolerance is a maximum IDO cancellation range that the analog DSL can remove. It is determined by the maximum output swing range of the DSL integrator (VDSL,MAX), feedback capacitor of the analog DSL (CA-DSL), and the input capacitor (CIN). The IDO tolerance is expressed as follow.

IDO tolerance = C_A−DSL

C_IN · V_DSL,MAX (4.4)

Proper IDO tolerance must be secured in order for the CCIA to operate stably without output saturation. But, VDSL,MAX is limited to the supply voltage minus headroom voltage of the DSL integrator output. In order to widen the IDO tolerance, it is necessary to increase the CA-DSL, which causes a trade- off that also increases the HPF cutoff frequency.

Figure 4.3. (a) Conventional schematic of the LNA with analog DSL and (b) implementation of the duty-cycled resistor.

CINT RINT

CA-DSL

-1

CIN

C_FB

V

IN

V

_OUT

V_DSL Analog DSL

R0

fDSL Pulse

(duty-cycle = D)

D = (Inverter delay) · f

_DSL

R

INT

= R

0

/ D

(a) (b)

29

In this study, the VDSL,MAX is about 1.2V under the 1.8V supply voltage and 0.3V headroom voltages near the ground and supply voltage at each. The CA-DSL is determined as 150fF to set an IDO tolerance value to 30mV. In the condition where the CIN, CFB, and CA-DSL w determined, integrator resistor (RINT) and capacitor (CINT) must be increased to lower the HPF cutoff frequency, but the CINT is designed to be 8pF in consideration of the chip size. A duty-cycled resistor, shown in figure 4.3(b), is used that can be adjusted with less process variation while obtaining a large resistance value in a small area. Using a short pulse which has a duty-cycle of D and is generated from an input clock (fDSL) and logic gates, and the switch is turned on for only a very short time to obtain a very large equivalent resistance. A resistor (R0) and switch connected in series obtain a high equivalent resistance of R0/D.

Figure 4.4 shows simulated and measured frequency response of the LNA as shown in figure 4.3(a).

Both results were obtained under the same conditions and the input clock of the duty-cycled resistor (fDSL) was 0.75kHz. Despite the same conditions, the measurement result shows a higher HPF cutoff frequency than the simulation result. Despite the same conditions, the measurement result shows a higher HPF cutoff frequency than the simulation result, which is thought to be limited in obtaining a very high equivalent resistance by the parasitic capacitance in the switch of the duty-cycled resistor as described above. As an additional reason, it is believed that the HPF cutoff frequency increased as the inverter delay increased more than the simulation due to process variation. It is possible to decrease the fDSL in the measurement to lower the HPF cutoff frequency, but arbitrarily configured fDSL can cause signal aliasing with the LNA chopping clock. Therefore, in chapter 4.2.1.2, a structure that lowers the HPF cutoff frequency even more by using an attenuator is proposed.

Figure 4.4. Simulated and measured frequency response of the LNA using a duty-cycled resistor.

f_hp,meas≈ 1.4Hz

fhp,meas≈ 0.3Hz

30

Figure 4.5(a) shows the simplified LNA schematic for noise analysis of the core amplifier and the DSL amplifier. Vni,CORE and Vni,DSL are input-referred noises of the core amplifier and the DSL amplifier respectively. The input-referred noise of the LNA which is caused by the Vni,core and the Vni.DSL are expressed in equation (4.5) and (4.6).

V_ni² = V_no²

A_V² = (C_IN+ C_FB+ C_A−DSL

C_IN )

2

· ( 1 1 + (w_hp/s))

2

· V_ni,CORE² (4.5)

Vni2 = V_no²

AV2 = (C_A−DSL C_IN )

2

· (1 + (1/sR_INTC_INT) 1 + (w_hp/s) )

2

· Vni,DSL2 (4.6)

where the pass-band gain (AV) and HPF cutoff frequency (whp) of the LNA are noticed in equations (4.2) and (4.3). Assuming that the RINT and CINT are sufficiently large, the input-referred noise from the Vni,DSL

can be simplified as an equation (4.7).

V_ni² = (C_A−DSL C_IN )

2

· ( 1 1 + (w_hp/s))

2

· V_ni,DSL² (4.7)

In general, the CIN has a much larger value than the CFB and CA-DSL, so when comparing equations (4.5) and (4.7), the input-referred noise of the LNA is much more affected by the noise of core amplifier than the DSL amplifier. Therefore, it is designed to modulate the noise of the core amplifier to a high frequency in the implementation of chopper stabilization.

Figure 4.5(b) shows the simplified LNA schematic for offset analysis of DSL amplifier, where the Vos,DSL is input offset of the DSL amplifier. The LNA output offset (Vos,OUT) caused by the Vos,DSL is

Figure 4.5. Schematic of the CCIA for (a) noise analysis and (b) offset analysis of the core amplifier and DSL amplifier.

C_INT RINT

CA-DSL

-1

CIN

CFB V_os,DSL

V

os,OUT

(a) (b)

CINT R_INT C_A-DSL

-1

C_IN

C_FB V_ni,DSL

V

no Vni,CORE

31 expressed by the following equation (4.8).

V_os,OUT = C_A−DSL

C_FB · 1 + (1/sR_INTC_INT)

1 + (w_hp/s) · V_os,DSL (4.8)

Because the Vos,DSL is induced from the fabrication process mismatch and it exists on zero frequency (s=0), the simplified equation can be expressed in equation (4.9).

V_os,OUT = C_A−DSL

C_FB · C_FB

C_A−DSL · V_os,DSL= V_os,DSL (4.9) As a result, the DSL amplifier offset is transferred to the LNA output. Since the DSL amplifier is designed in a fully differential and symmetric structure, the Vos,DSL is quite small, so this part is not a critical problem in the CCIA design.