r,-V-1t
THE DESIGN OF AN ECONOMICAL H]GH SPEED INTERFACE BET\,ÙEEN THE CIRRUS COMPUTER AND THE CHEMTCAL
ENGINEERING PROCESS CONTROL LABORATORY
L. J. Dunne B.Sc. (Adel-aide 1947)
Depai:tment of Chemical Engineeritg, Facul-ty of Engineening,
Univer:sity of Adelaide
Novemben, 1969.
5
fJth September, 19TO.
The RegÍstrar,
The University of Ad.elaide,
. S.,lLo 500û
Dear Sir,
r hereby give consent to the loan of or photocopyi'g of the thesis rtlrhe Design of a lligh speed computer rnterfacer as
requiredo
Yours faithfully,
(¿. ûrnne)
STATEI"ÍENT
The design as set out in the attached thesis was ca:rrj.ed
out independently by the undersigned while a post gnaduate
student in the Department of Chemical Engineening at the
Univensity of Adel-aide. The matenial descnibed has not been
accepted fon the award of any othen degr:ee on diploma in any
Univensity. Due acl<nowledgement has been made in the
bibliognaphy of all infonmation upon which the design was
based.
(L. J. Dunne)
i
l
SI.IMMARY
This thesis descnitres t-he design and constnuction of a sinple interface equipment 'to at.tow tfre use of CIRRUS, a smal-l-
rnícro-pnogrammed digital computen, as a control- element in dj-rect digital contnol of Chemical Engineering Process Contnol expei:iments in the laborafory.
Conversion of up to B anaÍogúe volt-ages, these being the ou-Lputs of transducens measuning parcÌrneters in the process, intct
di6¡ital fonm and transmitting these data to the computer is carnied out in 1 msec. After. processing in the computer, up to B digital quantities can be returned to the interface where they
are conver-te.cl into analogue form fon o1>erating the cont-nol.
mechanisms in the pnocess. This whol-e operation, conversion, computation and return ancl reconver-sion, is possible at sampl-ing nates of up to 100 samplcs pen second. The ac-tual- sampling nate
is, of coulrse, dependent on the compl-exiby of the process and
control- comput-ation being camied out. fn all- openations the conversions alre made to an accunacy of 9 binary digits (f pa:r-L in 512) this being co:npatible with the basic accunacy of the
majonity of the pnocess tiransducells and ac-Luators with r^¡hich the ec¿uipment will be associated.
Extensive use has been made of micr.oefectncnics in the
realisat j.on of the equipment. This has nesulted in an inte::face of high speed, small physical size, high rel-iabil-ity, and at a reasonable capital- cost.
While the equipment has been designed initially fon the computen CIRRUS, the design of the interface is general in cha::acter:, and, with small modification, should be capable of
wonking compatibly with many of the general- purpose cligital- computers ava:'-Ial¡fe now.
ACKNO\MLEDGEMENT
The author wishes to sincerely acknowledge the encouragement and support of Professor R,'W. F. Tait, the Professor of Chemical Engineering at the University of Adelaide, and all members of the academic staff of that Department. In particular, he would like to thank Mr. C. P. Jeffreson, a Senior Lecturer in the Department, for his patience, encouragement and assistance throughout the project.
The contributions of the following Staff members of the University of Adelaide are
"1"o g""tefully acknowledged : -
Mr. V. Rendall for the initíal testing and assessment of perform- ance of the many circuits used in the interface.
Mr.' R. Nash for the early checking of the logic hardware of the system.
.Mr. M. Hutchison who painstakingly checked the wiring and the operation of the interface as a whole.
Dr. R. Potter for discussions on how best to control the interface - computer system and for the digital data transmission technique used.
Messers B. Ide, R. Geisecke, and c. 'wood for their many helpful suggestions throughout the project.
1 2
CONTENTS
Intnoduction
System Specification
2 .1. General
2.2. Speed and Accuracy
2.g. Data Transmission
2.4. Digital Data Formats
Design Philosophy
3.1. General, Data Transmission, Data
fonmat and Control 3.2. The Multiplexer
3.3. The Digital to Analogue Conventens
3.4. Analogue to Digital Convension 3. 5. Equiprnent Realisation
Descniption of the Interface Unit
Hardwane
4.1. The Texas Tnstruments 74 seríes Integrated Circuit System 4.2.
4.3.
4.4 .
4.5.
4.6 . 4.7 .
4.8 . l+.9.
The Multiplexer
fhe Di8ital to Analogue Conventers The Analogue to Digital Converten The Timing Genenaton
The Intenface Control ].ogic
Data Tnansmission Powe:: Supplies
Construction of the Interface
Equipment
Page Numben
I
16 3B
+7 56
60
60 75 85 97 110 116 133 140
1
5
5 6 6 7
I
3
4.
153
CONTENTS (Contrd)
5. Penformance Achieved
5.1. The MultiPlexer
5.2. The Digital to Analogue Convertens 5.3. The Analogue to Digital Conventen
5 .4 . Control Logic ,Timing Ûnits and
Checking Cincuits
, 5.5. The Data Tnansmission Cincuits 5.6. The CaPital Cost
6. Conclusion
Appendix - A. An AnalYsis of the More
Common Sounces of Erron in the Solid State Openational AnPlifien
Bibliography
TLLUSTRATTONS
Figune 1.1. A Typical Real Time Computen Contnbl
System
Data Flow between Interface and
Computer
Layout of Conversion Sequence Balanced Diode Switches
Simple Transistor Switches
Equivalent Circuit of the Switching Tnansiston (Invented Connection) Balanced Transiston Switches
The Junction Field Effect Transiston
The MOST Metal-Oxide-Semi conductor
Tnansistor (rrNrr Channel)
3 .1.
Page Numben 1s6 156 L57 157
158 159 1s9 161
164 176
13 15
2l
23
3
2,
3.3:
3.4.
3.5 .
3.6.
3.7.
3.8.
26 29 31
3.9. A Simple FET Commutator 36
ILLUSTRATIONS (Cont rd)
Figure 3.10.
3.11.
3.12.
3.13.
3.14 . 3.15 .
3.16.
3.L7 .
4 .1.
t+.2.
4 .3.
4.4.
4 .5.
4.6.
4.7 .
4.8.
4. 9.
4.10.
4 .11.
4.I2.
4.13.
4 .14.
4.15.
Digital to Analogue Converters
Ladden Netwo::ks - Voltage Switching
Digital to Analogue Conventens
Ladder Netwonks Cunrent Switching A Simple Diode Curuent Switch
Ramp type A-D Encoder
The Voltage to Fnequency A-D Encoder Continuous Balance A-D Encoder
Successive Approximation A-D Ëncoden
Legàna of Logic Symbols to U. ,r""¿
The 74 Senies Element
The Simple Eig. De1ay Circuit Pulse Fonming Cincuit
Pulse Delay Cincuit Vaniant of Pulse Delay
Delay versus Capacity for Delay
Circuits
The 74 series Micnocincuit Mounting Cands
The Multiplexen
lrlaveforms Multiplexen Logic Commutator Switch Schematic The Multiplexen Card
the Digital to Analogue Conve::ten
The Digital to Analogue Converter Cand The Analogue to Digital Converter
The Astable Clock Genenaton
Page Numben
40
41
t+5
48 50 51 53 59 61 66 69 70 72
73
74 76 78 80 86 89 98 100
r02
ILLUSTRATIONS (Cont rd)
Figune 4.16. V'lavefonms - Analogue to Digital
Converten
4.L7. The Analogue to Digital Conventen Cand
Page Numben
109
111 113 11+
115
r20, 1,
]-23
]24
130 L32
13 t+
136 139 141 144 145 147 149 150 l.52 154 155 165 165
4.18.
4.19.
4 .20.
4.2l..
+ .22.
4 .23.
+.24 . 4.25 . 4.26.
4.27 .
4.28.
4.29.
4.30.
4. 31.
4 .32.
4.33:
4.34.
4.35.
4.36.
4.37.
4.1.
4.2.
Timing Generator Schematic
Timing Generaton -Deiail
!'laveforms Timing Generator:
pata Flow Diagnam, Control Logic
Logic Schematic of the Interface
The Control Logic Hardwane Control Logic lrlavefonms
Parity Generaton
Panity Check
Data T::ansmittens
Data Receivens -
Data Transmission Cards Power Supply Schematic
Basic Raw Supplies The +5V Log; s Supplies The Positive Regulators The Negative Regulatons The Reference Supplies
Fnont View - The Interface Unit Card Mounting - The Intenface Unit The Operational Arnplifien
The Inventing Arnplifier
2
Figure
