COUNTERS AND COUNTERS AND REGISTERS

Chapter 7

COUNTERS AND COUNTERS AND

REGISTERS REGISTERS

Instructor: Afroza Sultana

Asynchronous (ripple) Counters

• Each FF output drives the clock input of the next FF This

• Each FF output drives the clock input of the next FF. This type of counter is called Asynchronous counter.

• The FFs do not change states in exact synchronism with the applied clock signal.

• There is a delay between the response of successive FFs.

Frequency Division

f f/2 f/4 f/8 f/16

In any counter, the signal at the output of the last FF(i.e., the MSB) will have a frequency equal to the input clock frequency divided by the MOD number of the counter.

Asynchronous Down Counter

Counting Sequence

C B A 1 1 1 1 1 0 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 1 0 0 0

MOD Counters

• MOD Number: The MOD no is equal to the no of states that the counter goes through in each states that the counter goes through in each complete cycle before it recycles back to its starting state.

• The MOD no can be increased simply by adding more FFs. That is

MOD no = 2^N MOD no = 2^N

where N is the number of FFs^.

• Counters can be designed having MOD no <2^N.

Counters with MOD Numbers < 2

^N

Th b i h t i li it d t MOD 2^N

• The basic asynchronous counter is limited to MOD no = 2^N.

• The Basic counter can be modified to produce counter with MOD no < 2^N by allowing the counter to skip some states.

MOD-6 counter produced by clearing a MOD-8 counter when a count of six occurs.

Counters with MOD Numbers < 2

^N

• A NAND gate is connected to the asynchronous clear inputs of each FF so that counter immediately goes to inputs of each FF so that counter immediately goes to the 000 state.

• The counting sequence is , thereforeg q , C BA

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1

1 1 0 (temporary state)

Changing the MOD number

MOD-10 (decade) ripple counter

MOD-14 ripple counter

Propagation delay in ripple counters

Problems in using Ripple Counter

• For proper counter operation, we need clock time T_clock ≥ N X t_pd

where N= no of FF

d th l k f

and the max clock frequency

f_max = 1 / (N × t_pd )

• Asynchronous counters are not useful at very high frequencies, especially for large number of bits.

Synchronous (Parallel) Counters

ƒ All FFs are triggered simultaneously by the clock input pulses

ƒ All FFs are triggered simultaneously by the clock input pulses.

ƒ Overcome the problem caused by FF propagation delay.

ƒ Only the LSB ff has its J and K inputs permanently HIGH.

ƒ Requires more circuitry than does the asynchronous counter.

Circuit operation

• Only those FFs that are supposed t t l th t NGT h ld h

to toggle on that NGT should have J=K=1 when that NGT occurs.

• Each FF should have its J and K

i t t d th t th

inputs connected so that they are HIGH only when the outputs of all

l d FF i th HIGH t t

lower-order FFs are in the HIGH state

Counters with MOD Numbers < 2

^N

Advantage of Synchronous counters h

over Asynchronous

• States are changed simultaneously.

• The propagation delays of the FFs do not add together to produce the overall delay.

• Total delay = FF t_pd + AND gate t_pd

• The total delay does not depend on the no of FFs.

Synchronous Down and UP/Down Counters

Presettable Counters

Presettable Counters

• When the counter can be preset to any desired starting count either asynchronously or asynchronously.

• The asynchronous PRESET and CLEAR inputs are used to perform asynchronous presetting.

• Apply desired count to the data inputs PApply desired count to the data inputs P₂₂, P, P₁₁ and Pand P_00.

• Apply a LOW pulse to the input PL.

• This procedure will perform an asynchronous transfer of P₂, P₁ and P₀ levels into FFs Q₂, Q₁ and Q₀.

• This jam transfer occurs independently of the J, K, and CLK inputs.

• The effect of the CLK input will be disabled as long as PL is in its

• The effect of the CLK input will be disabled as long as PL is in its active-LOW state because each FF will have one of its

asynchronous inputs activated while PL=0.

• Once PL returns HIGH the FFs can respond to their CLK inputs and

• Once PL returns HIGH, the FFs can respond to their CLK inputs and can resume the counting up operation starting from the count

that was loaded into the counter.

IC Registers IC Registers

• Registers can be classified by the way data is entered for storage, and by the way data is ouputted from the register

ouputted from the register.

– Parallel In / Parallel OutParallel In / Parallel Out (PIPO)(PIPO) – Serial In / Serial Out (SISO) – Parallel In / Serial Out (PISO) – Serial In / Parallel Out (SIPO)

Parallel In / Parallel Out

PIPO (74ALS174)

Serial In / Serial Out

• A serial in/serial out shift register will have data loaded into it one bit at a time.

• The data will move one bit at a time with each clock pulse through the set of flip-flops toward the other end

f th i t of the register.

• With continued clocking, the data will then exit the register one bit at a time in the same order as it was register one bit at a time in the same order as it was originally loaded.

Serial In / Serial Out

Th 74HC166 ( d l th 74ALS166) b d

Serial In / Serial Out

• The 74HC166 (and also the 74ALS166) can be used as a serial in/serial out register.

• It is an eight-bit shift register of which only FF QIt is an eight bit shift register of which only FF Q_HH isis accessible.

• The serial data is input on SER and will be stored in FF Q

Q_A.

• The serial output is obtained at the other end of the shift register on Q_H.

register on Q_H.

• Parallel data can also be synchronously loaded into it.

• If SH/LD= 1, the register function will be serial shifting, while a LOW will parallel load data via the A through H inputs.

• The synchronous serial shifting and parallel loading

• The synchronous serial shifting and parallel loading functions can be inhibited (disabled) by applying a HIGH to the CLK INH control input.

Parallel In / Serial Out

PISO (74HC165) PISO (74HC165)

Serial In / Parallel Out

SIPO (74ALS164)