Introduction
Under ideal sinusoidal grid conditions, the SRF-PLL operates effectively at a very high bandwidth, providing fast and accurate phase angle estimation. The presence of harmonics in grid voltage is a major cause for inaccurate phase angle estimation. This thesis aims to develop a signal reformation algorithm that can reform the three-phase unbalanced grid signal with amplitude and phase imbalances into the three-phase balanced signal without discarding the information about amplitude and phase angle of the original voltage signal.
Using a traditional harmonic filter changes the phase angle of the filtered signal, causing an error in the phase angle estimation. Information about the phase angle imbalance between two phases was also extracted using this algorithm. The PLL phase detector was implemented based on the Clark and Park transform [99].
The fundamental frequency obtained from the output of the loop filter is integrated to obtain the phase angle of the reference phase voltage.
Phase-Locked Loops
- Single-Phase Inverse Park PLL
- Single-Phase Second Order Generalized Integrator Based PLL
- Single-Phase Transport Delay PLL
- Three-Phase SRF-PLL
- Dual Second Order Generalized Integrator PLL
The VCO adjusts its own frequency until it equals that of the input signal. At that point, the frequency and the phase of the input and output signals are synchronized, with or without a constant phase difference. The last term on the right-hand side of (3) is suppressed by the loop filter of the PLL.
The estimated phase angle is synchronized with the instantaneous phase angle of the power grid once the q-axis component is driven to zero. 14 The integrators represent two second-order filters with an adjustable bandwidth and resonant frequency equal to the frequency of the input signal. These DC components collect information about the amplitude and phase angle of the positive and negative sequence components of the mains voltage vector.
This voltage is translated to the rotating SRF and the signal on the q-axis is applied at the input of the loop controller and the fundamental grid frequency and phase angle of the positive sequence voltage is estimated. The value of vq is regulated to zero and the phase angle of the grid voltage, θ is estimated. It shows that the conventional SRF-PLL cannot estimate the phase angle of a three-phase system when the amplitudes of the phases are not equal, although the phase angle differences are unchanged.
22 The conventional SRF-PLL was tested for the unbalanced conditions when the amplitudes of the three phases are equal while the phase angle differences between the phases are changed. Under such distorted conditions, the SRF-PLL can still be developed to accurately estimate the phase angle at reduced bandwidth to perform proper filtering by the PI controller of the PLL. 24 Fig 2.14 and Fig 2.15 show the performance of the SRF-PLL under harmonic affected conditions at high and reduced bandwidth respectively.
26 Figure 2.17: Performance of the conventional SRF-PLL in the presence of harmonics under both unequal amplitude and unequal phase differences between the phases at low bandwidth (a) three-phase voltage waveforms; (b) vq versus time; (c) estimated phase angle of va. In both cases, the conventional SRF-PLL inaccurately estimated the phase angle of the three-phase system.
The Developed Phase-Locked Loop
A harmonic attenuation technique, which is much simpler than any filter algorithm, has been developed so that the three-phase input signal can be refined by attenuating the amplitudes of the higher order components. The filter block reduces the amplitudes of the harmonic components of the input grid voltage signals, so that the zero crossing points and peaks can be determined and the signal reforming block can easily reform the signal. Here the superscripts on the amplitudes of the harmonic components indicate their amplitudes after the number of unit blocks as the superscripts mention.
The value of hmax is the maximum order of the harmonics assumed to be predominant in the signal. Here, 𝑎11 and 𝑎ℎ1 denote the amplitude of fundamental and harmonic components, respectively, after passing through the first block. The block diagram of a single unit of the harmonic damping system is shown in Fig.
For attenuation of hth harmonics, the transfer function of the block diagram in Fig. After the signal has been passed through each additional block in the filtering stage, the refined signal is used to calculate the frequency and phase angle using the developed PLL algorithm. As determined from the calculation, the errors are reduced with the increase of the number of blocks.
Any ordinary filter will require the information of at least one period of the signal which is not admissible for the operation of the SRF-PLL. However, if the frequency of the harmonic component is greater than the nominal frequency, the proposed method will gradually deviate from accuracy. The information about the estimated frequency is fed back to the filter units and the filters update the ωe of the 𝜔𝑒2ℎ𝑚𝑎𝑥2 divisor with the modified frequency.
First, one of the phases of the three-phase system is selected as the reference signal. The efficiency and performance of a PLL depends on the performance of the loop filter.
Simulation Results
Case-A1: Voltage Sag at All the Phases
In this case, all three phases of the 220 Volt, 50 Hz three-phase balanced grid voltage suffer from voltage sag. 4.1(c) is the vq vs time curve, showing that the recovery time of the PLL under this condition is 0.0285 seconds. In this case, similar to case-A1, all three phases of the 220 Volt, 50 Hz three-phase balanced grid voltage suffer from voltage swell.
In this case, the three-phase system has suffered voltage drops in two of the phases and voltage fluctuations in one phase. In this case, only one of the phases of the 220 Volt, 50 Hz three-phase balanced system suffers from sudden phase shifts at 0.1 second. 47 Figure 4.5: Performance of the developed PLL with sudden phase shift of phase-c. a) three-phase voltage waveforms; (b) three-phase voltage waveforms after reforming.
It is also possible that all three phases of the system have shifted from their positions. 4.2.6: Case A6: Simultaneous amplitude imbalance and phase shift of all phases In this case, the three-phase 220 Volt, 50 Hz system has both the unequal amplitude and unequal phase angle differences of the phases. This means that the maximum amplitudes of the three phases are equal and the phase angle differences between the phases are 120°.
The performance is demonstrated in fig. 4.11, and the recovery time of the PLL for accurate phase angle estimation is 0.0262 seconds. Hz three-phase system suffers from a sudden frequency drop of 5 Hz at 0.1 second simulation when the system's phase angle differences also change. Hz three-phase system suffers from a sudden frequency jump of 5 Hz at 0.1 second simulation when the system phase angle differences also change.
The amplitudes of the three phases remain correctly balanced. 4.13 shows the performance of the developed PLL under this condition. It shows that the PLL can successfully estimate the phase angles of the system within 0.0109 second after perturbation.
Case-B1: Balanced System Distorted by Harmonics
61 Figure 4.17: Performance of the developed PLL under harmonic-affected conditions (IEEE 519-2014 standard) with a balanced system (a) three-phase voltage waveforms; (b) three-phase voltage waveforms after reformation; (c) vq versus time; (d) estimated phase angles of va, vb. In this case, the performance of the developed PLL is observed when all phases of the system suffer from voltage drop in the presence of harmonics. The performance of the developed PLL is observed when all phases of the system suffer from voltage rise due to the presence of harmonics.
64 Figure 4.22: Performance of the developed PLL under harmonic affected condition with phase shift of phase-c (a) three-phase voltage waveforms; (b) three-phase voltage waveforms after reforming;. In this case, the balanced three-phase system suffers from phase shift of all the phases and is affected by harmonics at 0.1 second. 4.23 shows the performance of the developed PLL when phase-b and phase-c suffer from phase shift of 20° and 50° respectively. The performance of the PLL is demonstrated in Fig. 4.24 which shows that it can estimate the phase angles of all the phases within 0.038 seconds.
In this case, the performance of the developed PLL is observed when the network is affected by harmonics and operates at a frequency lower than the nominal value. The maximum permissible amplitudes of the harmonic components are determined according to the IEEE 519-2014 standard. 4.25 shows the performance of the developed PLL at the standard affected by harmonics. 71 4.2.10: Example B10: Phase shift of phases with harmonic distortion at a frequency other than the nominal value.
The phase angle differences of the system are also changed, while the amplitudes of the three phases remain well balanced. 4.29 shows the performance of the developed PLL during this condition. It shows that the PLL can successfully estimate the phase angles of the system within 0.0322 second. The three-phase system affected by Hz harmonics experiences a sudden frequency jump of 5 Hz at 0.1 second of simulation, when the phase angle differences of the system are also changed.
The amplitudes of the three phases remain correctly balanced. 4.30 shows the performance of the developed PLL under this condition. 74 Figure 4.32: Performance of the developed PLL under unbalanced and distorted condition at higher than nominal frequency. a) three-phase voltage waveforms; (b) three-phase voltage waveforms after reforming.
Conclusions
Block Diagram of the Whole System for Simulation
The entire setup for simulation and analysis of the results consists of a programmable three-phase voltage source, a three-phase filter block, a signal reformer block, an SRF-PLL block that combines the rotary transform block and the PLL block, and a phase-evaluation block of angle to estimate the phase angles of all phases.
Block Diagram of the PLL Block
The filter block for each stage is developed by sequentially cascading 24 sets of unit filter blocks.
MATLAB Code for Three-Phase Grid Voltage
![Fig. 2.1 shows the block diagram of a typical PLL [100]. The operation of the PLL is similar to that of a feedback system](https://thumb-ap.123doks.com/thumbv2/filepdfnet/10874253.0/34.893.184.708.723.942/fig-shows-block-diagram-typical-operation-similar-feedback.webp)
