Paolo IDF session 030305

(1)

Intel

’

s Si l i con Power

Savi ngs Strategy

Keepi ng Moore

’

s Law Al i ve and Wel l

Paolo Gargini

Intel Fellow and

Director, Technology Strategy

(2)

2

*Third party marks and brands are the property of their respective owners

Agenda

y

Moore

’

s Law and scaling

y

The power challenge

y

(3)

3

Agenda

y

Moore

’

s Law and scaling

y

The power challenge

y

(4)

4

“

Reduced cost is one of the big

attractions of integrated

electronics, and the cost

advantage continues to increase

as the technology evolves

toward the production of larger

and larger circuit functions on a

single semiconductor substrate.

”

Electronics, Volume 38,

Number 8, April 19, 1965

1960

1965

1970

1975

1980

1985

1990

1995

2000

2005

2010

Transistors

Per Die

10

8

10

7

10

6

10

5

10

4

10

3

10

2

10

1

10

0

10

9

10

Source: Intel

Moore

’

s Law

-

1965

1965 Data (Moore)

Moore’s Law

“

The new slope might

approxi

-

-mate a doubling every two years,

mate a doubling every two years,

rather than every year, by the

end of the decade.

”

Gordon Moore, 1975

(5)

5

Moore

’

s Law (functi ons per chi p)

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

1,000,000,000

10,000,000,000

1970

1980

1990

2000

2010

4004

8080

8086

8008

Pentium® Processor

486™ DX Processor

386™ Processor

286

Pentium® II Processor

Pentium® III Processor

Itanium® Processor

Pentium® 4

Processor

Itanium® 2 Processor

2X

/2Y

R

2X/1YR

(6)

6

Intel 486™

Processor

Pentium

®

Processor

Pentium

®

II/III

Processor

Pentium

®

4

Processor

1.0µm 0.8µm 0.6µm 0.35µm 0.25µm 0.18µm 0.13µm 90nm

Moore

’

s Law i n Acti on:

Mi croprocessors Advance

Process + architecture innovations

Source: Intel

(7)

7

Manufacturi ng Leadershi p: Scal e,

Agi l i ty and Excel l ence

Wafer Starts / Week

(200mm Equiv.)

0.6

µ

m

0.35

µ

m

0.25

µ

m

0.18

µ

m

0.13

µ

m

90 nm

65 nm

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005

Each process generation ramps faster and higher

(8)

8

Intel

’

s 90nm Process Yi el d Improved

at Record Rate

1998

1999

2000

2001

2002

2003

2004

Defect

Density

(log scale)

0.18

µ

m

200mm

0.13

µ

m

200mm

0.13

µ

m

300mm

90nm

300mm

(9)

9

Average Transistor Price by Year

Nearly 7 Orders Of Magnitude Reduction in Price/Transistor

0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

10

'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02

100 Nanodollars per transistor !

Source: WSTS/Dataquest/Intel, 3/04

(10)

10

Si l i con Technol ogy Reaches Nanoscal e

Micron

10000

1000

100

10

1

0.1

0.01

Nano

-

-meter

meter

Nanotechnology

(< 100nm)

130nm

90nm

70nm

50nm

Gate Length

65nm

35nm

1970

1980

1990

2000

2010

2020

45nm

32nm

22nm

25nm

18nm

12nm

0.7X every

2 years

Nominal feature size

Source: Intel

Micron

10000

1000

100

10

1

0.1

0.01

Nano

-

-meter

meter

Nanotechnology

(< 100nm)

130nm

90nm

70nm

50nm

Gate Length

65nm

35nm

1970

1980

1990

2000

2010

2020

45nm

32nm

22nm

25nm

18nm

12nm

0.7X every

2 years

Nominal feature size

(11)

11

Li thography Must Break Through

to Shorter Wavel ength (EUV* @ 13.5nm)

* Extreme Ultraviolet

Source: Intel

1000

100

10

’

89

’

91

’

93

’

95

’

97

’

99

’

01

’

03

’

05

’

07

’

09

’

11

Feature size

EU V

Lithography

Wavelength

193nm & extensions

248nm

nm

Gap

(12)

12

Figure 14 Critical Level Resist Technology Potential Solutions Roadmap

Semiconductor Industry Association.

The National Technology Roadmap for Semiconductors, 1994 edition

. SEMATECH:Austin, Tx, 1994.

1994 NTRS

EUV

F u r t h e r S t u d y R e q u i r e d L e a d i n g - E d g e P r o d u c t i o n

P i l o t L i n e D e v e l o p m e n t / M o s t L i k e l y P a t h

B a c k U p

2 0 0 4 1 9 9 2

1 9 8 9 1 9 9 5 1 9 9 8 2 0 0 1 2 0 0 7 2 0 1 0

E n v i r o n m e n t , S a f e t y , a n d H e a l t h i m p a c t r e d u c t i o n : s a f e r s o l v e n t s , w a t e r s o l u b l e , d r y p r o c e s s i n g , e t c .

H i g h s e n s i t i v i t y a l t e r n a t e c h e m i s t r i e s ( N o n - a c i d c a t a l y z e d )

0 . 3 5 m m G e n e r a t i o n

2 4 8 n m D U V I - L i n e

0 . 2 5 u m G e n e r a t i o n 1 X X - r a y

s i n g l e l a y e r

2 4 8 n m D U V w / e n h a n c e m e n t s

N a r r o w o p t i o n s t o o l -b a s e d

0 . 1 8 u m G e n e r a t i o n

2 4 8 n m s i n g l e l a y e r & A R C 1 9 3 n m s i n g l e l a y e r & A R C 1 X X - r a y s i n g l e l a y e r 1 9 3 n m s u r f a c e i m a g i n g N X I o n p r o j e c t i o n

E U V

1 X X - r a y

N a r r o w O p t i o n s t o o l - b a s e d N X E - b e a m p r o j e c t i o n

N X I o n P r o j e c t i o n E - b e a m h i g h t h r o u g p u t

0 . 1 0 u m G e n e r a t i o n N X E - b e a m p r o j e c t i o n

A d v a n c e d R e s i s t S y s t e m s

0 . 1 0 u m G e n e r a t i o n N a r r o w

O p t i o n s t o o l - b a s e d 1 9 3 n m

N X I o n P r o j e c t i o n E - b e a m h i g h t h r o u g p u t

1 X X - r a y

N X E - b e a m p r o j e c t i o n

(13)

13

EUV Li thography i n

Commerci al Devel opment

EUV Micro exposure tool (MET)

EUV MET Image (8/04)

Integrated development in progress

y

Source power and lifetime

y

Defect free mask fabrication and handling

y

Optics lifetime

y

Resist performance

Source: Intel

(14)

14

EUV Source Power Increased

0.1

1

10

100

1000

Jul

Jul-

-01

01

Jan-

Jan

-02

02

Jul-

Jul

-02

02

Jan-

Jan

-03

03

Jul-

Jul

-03

03

Jan-

Jan

-04

04

Jul-

Jul

-04

04

Jan-

Jan

-05

05

Jul

Jul-

-05

05

Jan-

Jan

-06

06

EUV Power at Intermediate Focus [W]EUV Power at Intermediate Focus [W]

115 W Production Requirement

Exponential fit to data

Average of reported data

(SEMATECH Source Workshops)

Source: SEMATECH

(15)

15

0.001

0.01

0.1

1

Jan-04

Apr-04

Jul-04

Sep-04

Dec-04

P

ro

c

ess ad

d

e

d

e

fect

d

e

n

s

it

y

@

80n

m

sen

s

it

iv

it

y (

c

m

-2)

EUV Mask Bl ank Defects Reduced

Only 1 added

defect!

Goal

Target for production @ 32nm

Results from SEMATECH

Source: SEMATECH

(16)

16

Cost/ Pi xel Trend w/ Tool Cost Ranges

(Source:

Intel ’03)

Cost/ Pi xel Trend w/ Tool Cost Ranges

(Source:

Intel

’

03)

Cost/ Pi xel normal i zed to 90nm Node

Tool Cost Ranges based on 2002 ISMT Exposure Tool Cost Survey Resul ts

Cost/ Pi xel normal i zed to 90nm Node

Tool Cost Ranges based on 2002 ISMT Exposure Tool Cost Survey Re

sul ts

0.001

0.01

0.1

1

10

100

1990

1995

2000

2005

2010

2015

Normalized Cost/Pixel)

(17)

17

Transistor Trade-offs

F

Max

= I

DSat

/ V

DD

C

ox

I

DSat

~1

µ

C

ox

(W)(V

DD

–V

T

)

2

Lg

Power= V

DD

2

C

ox

F

Max

S

D

G

Lg

W

Increase Cox

=>Reduce

t

ox

Reduce

Lg

Reduce

V

DD

ε

o

ε

s

(18)

18

Gate Oxi de Scal i ng

1

10

1990

1995

2000

2005

Gate Oxide

Thickness

(nm)

1

10

1.2 nm

90nm

.13um

.18um

.25um

.35um

Generation

I

DSat

1

µ

(V

DD

–V

T

)

2

Lg

W

ε

o

ε

s

1

t

ox

~

(19)

19

*T

h

ir

d

pa

rt

y

ma

rks

and

b

rand

s a

re

the p

rope

rty

o

f the

ir

r

e

spe

c

ti

ve

ow

ne

rs

Gate Delay Trend

100nm

F

Max

= I

DSat

/V

DD

C

ox

(20)

20

Transi stor Performance

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1990

1995

2000

2005

Drive

Current

(mA/um)

1

10

Supply

Voltage

(V)

NMOS

PMOS

1.2V

90nm

.13um

.18um

.25um

.35um

Generation

I

DSat

1

µ

(V

DD

–V

T

)

2

Lg

W

ε

o

ε

s

1

t

ox

~

(21)

21

The Incredible Shrinking

Silicon Technology in the 90s

0.35

µ

Gate

Salicide

Spacer

Salicide

1995

µ

0.25

Salicide

Gate

Spacer

Salicide

1997

0.18

µ

Gate

Spacer

Salicide

1999

(22)

22

New Transistor Trade-off

I

DSat

~1

µ

C

ox

(W)(V

DD

–V

T

)

2

Lg

S

D

G

Lg

W

Increase Cox

Reduce

Lg

µ

(23)

23

Strai ned Si l i con Transi stors

Normal Silicon Lattice Strained Silicon Lattice

Current Flow

Normal

electron

flow

Faster

electron

(24)

24

High

Stress

Film

NMOS

SiGe

PMOS

Compressive channel strain Tensile channel strain

30% drive current increase 10% drive current increase

Intel Produces Power Effi ci ent 90nm

Transi stors wi th Strai ned Si l i con

Innovate and integrate

for cost effective production

Source: Intel

(25)

25

65nm Technol ogy Hi ghl i ghts

y

Intel 65 nm generation logic technology provides

improved performance and reduced power:

–

1.2 nm transistor gate oxide

–

35 nm transistor gate length

–

Enhanced strained silicon technology

–

8 layers of copper interconnect

–

Low

-

k dielectric

y

This technology is being demonstrated on fully

functional 70

Mbit

SRAM chips with >0.5 billion

transistors

y

Intel

’

s 65 nm technology is on track for delivery in

2005

(26)

26

Gate oxi de scal i ng has sl owed

Source: Intel

The power

challenge

I

DSat

1

µ

(V

DD

–V

T

)

2

Lg

W

ε

o

ε

s

1

t

ox

~

Mobi

lity

1

10

1990

1995

2000

2005

Gate Oxide

Thickness

(nm)

1

10

1.2 nm

0.5

µ

m

0.35

µ

m

0.25

µ

m

0.18

µ

m

0.13

µ

m

90nm

65nm

Slower scaling of one parameter can be

compensated by speeding up another

Tra

nsi

sto

r

per

for

(27)

27

65nm Process

-

Transi stor

Strained silicon enhanced for

performance and power efficiency

35nm

(28)

28

65 nm Generati on Interconnects

M8

M7

M6

M5

M4

M3

M2

M1

• Metal 8 layer is added for

improved density and performance

(1 more layer than 90 nm generation)

• Low-k carbon doped oxide

dielectric reduces interconnect

capacitance

(improved from 90 nm

generation)

• Interconnect capacitance is

reduced by use of low-k dielectric

and by ~0.7x line length scaling

• Lower capacitance improves

interconnect performance and

reduces chip power

(29)

29

130nm

90nm

65nm

200mm

300mm

2000

2001

2002

2003

2004

Defect

Density

(log scale)

Two Years

Defect Reducti on Trend

65 nm yield on same improvement rate with 2 years offset

(30)

30

Ful l y Functi onal Devi ces on Intel

’

s

65nm Process

Fully functional 70 Mbit SRAM

~110 mm

2

die size

>0.5 billion transistors

Yonah

(31)

31

Agenda

y

Moore

’

s Law and scaling

y

The power challenge

y

(32)

32

Power Chal l enges

y

Power challenges are neither new nor

fundamental

–

“

Will it be possible to remove the heat generated by 10

’

s

of thousands of components?

”

(Moore, 1965)

–

Intel

’

s 1

st

product 1969: bipolar 3101 64

-

b RAM

y

Intel takes a holistic approach

–

From device/process power innovations

–

Transistor optimization is a key to low

-

power

–

To solutions at the platform level and beyond

y

Intel continues to invest and innovate on Moore

’

s

Law

–

R&D and capital

–

Benefits to functions, performance/power, and cost

(33)

33

Si l i con Technol ogy Changes to

Increase Power Effi ci ency

Mid

-

1960

’

s: Bipolar, PMOS

Mid

-

1970

’

s: NMOS

Mid

-

1980

’

s: CMOS

Mid

-

1990

’

s: CMOS, Voltage scaling

Mid

-

2000

’

s: CMOS, Power efficient

(34)

34

Source: Intel, VLSI Technology Symposium 6/04

1

10

100

1000

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Transistor

Drive Current

(

mA

/um)

Transistor

Leakage

Current

(nA/um)

Std

Strain

Std

Strain

+25% I

ON

+10% I

ON

0.04x I

OFF

0.20x I

OFF

PMOS

NMOS

15

90nm Strai ned Si l i con Saves

Power @1.2V

5X to 25X reduction in transistor leakage power

(35)

35

65 nm Generati on Transi stors

y

1.2 nm gate oxide, 35 nm gate length for improved

performance

y

220 nm contacted gate pitch for improved density

y

NiSi for low resistance cap on gates and source

-

drains

y

Intel

’

s unique

uniaxial

strained silicon technology, first

introduced on the 90 nm generation, is further

enhanced on 65 nm transistors for improved

performance

y

At the 65 nm generation, strained silicon improves

performance ~30% relative to non

-

strain

(36)

36

1

10

100

1000

0.2

0.4

0.6

0.8

1.0

1.2

I

ON

(mA/um)

I

OFF

(nA/um)

PMOS

NMOS

90 nm

2002

2004

65 nm

2004

1.0 V

Improved Transi stor Performance

65 nm transistors increase drive current 10

-

15% with

enhanced strain

(37)

37

1

10

100

1000

0.2

0.4

0.6

0.8

1.0

1.2

I

ON

(mA/um)

I

OFF

(nA/um)

PMOS

NMOS

90 nm

2002

2004

65 nm

2004

1.0 V

Improved Transi stor Performance

65 nm transistors can alternatively provide ~4x leakage

reduction

No other company has matched these performance

-

leakage

capabilities

(38)

38

Strai ned Si l i con

y

Intel 90nm strain silicon has been in volume

production since 2003

y

Observed leakage reduction @1.2V

–

N

-

Channel

-

> 5X Reduction

–

P

-

Channel

-

> >5X Reduction

y

Intel 65nm technology has been successfully

demonstrated in 2004 using

“

2

nd

Generation Strained

Silicon

”

y

Observed a further leakage reduction @1.0V from

90nm process

–

N

-

Channel

-

> 4X Reduction

–

P

-

Channel

-

> >4X Reduction

(39)

39

Reduced Gate Capaci tance at 65nm

Gate

Substrate

Source

Drain

C

GATE

Power

Saving

Feature

• Gate oxide thickness is held constant at

1.2 nm to avoid increased gate leakage

• Gate capacitance (C

GATE

) reduced ~20%

due to smaller gate length (35 nm)

• Lower gate capacitance reduces chip

active power

(40)

40

Gate

Substrate

Drain

Source

Oxide

C

WIRE

C

GATE

Gate

Substrate

Source

Drain

C

WIRE

C

JUNCT

C

GATE

Lower Juncti on Capaci tance

Speeds up Ci rcui ts

(

1

- Cj/C total)

1

SOI reduces junction capacitance (under 5% of total),

but not gate or wire capacitance

(41)

41

Planar CMOS

Bulk CMOS vs. PDSOI

Gate

SiO

2

SiO

2

Silicon Substrate

Partially Depleted SOI

Gate

SiO

2

SiO

2

Silicon Substrate

Buried Oxide

Silicon Substrate

(42)

42

Intel Already Has the Lowest Junction

Capacitance (180nm data)

S. Tyagi, IEDM 2000

Intel achieves the industry’s lowest junction capacitance

without SOI, thereby avoiding the cost of SOI

The power

challenge

Intel

0.40

0.60

0.80

1.00

1.20

1.40

1.60

-0.5

0

0.5

1

1.5

Bias (V)

N+/PWell

P+/Nwell

Wang, EDL Oct.'00

Mehrotra IEDM '99

Imai, IEDM '99

Yoshimura, VLSI '00

Diaz, VLSI '00

Yeap, VLSI '00

Junction

Capacitance

(43)

43

• All 3 elements of SOI performance diminish with scaling

- Gain for 90nm node: 3-10% depending on history guardband

0.18um

130nm

90nm

F.O.=1 Inverter

16%

13%

11%

F.O.=4 Inverter

8%

7%

6%

3-Input NAND

20%

17%

14%

Average

15%

12%

10%

History Guardband

-5%

-6%

-7%

NET

10%

6%

3%

Analysis ignores interconnect load, which reduces SOI gain further

K. Mistry, VLSI 2000

Net Impact of SOI Goes Down wi th

Each Generati on

(44)

44

Intel

’

s bul k CMOS has extremel y l ow

Cj

y

Low

Cj

=~ 0.1 x C total

y

Gross performance

gain = 1/(1

-

0.1) =

11%

y

Net gain is low

y

Bulk substrate cost

much less

y

If

Cj

= ~0.25 x C total

y

Then, gross performance

gain = 1/(1

–

0.25) =

33%

y

Net gain is high

y

High

Cj

is indicative of an

under optimized bulk

CMOS process

(

1

- Cj/C total)

1

(45)

45

Si Substrate

Oxide

R

SD

R

JUNCT

R

GATE

BULK SOI

SOI reduces junction capacitance, but not gate or wire capacitance

Has SOI “solved” the leakage problem? “No”

• SOI eliminated junction leakage

• Junction leakage is < 5% of total leakage in Intel process

• Ioff of Intel Strained Silicon is >10x lower than any reported data,

Including SOI

R

GATE

(46)

46

Summary of Strai ned Si l i con vs. SOI

y

Intel 90nm strain silicon has been in volume

production since 2003

y

Partially depleted (PD)

-

SOI has no place on Intel

roadmap:

–

Intel has thoroughly evaluated costs/benefits

–

Is saving millions per year on substrate alone by avoiding SOI

–

Cost adder is 15% or more

–

Performance benefit is less than 5% at 90nm

y

Intel demonstrated transistors with world

-

leading

performance/leakage characteristics:

–

Low

-

junction

-

capacitance bulk CMOS at 130nm

–

Uniaxial strained silicon at 90nm and beyond

y

Fully depleted (FD)

-

SOI (e.g. Tri

-

gate) has been under

evaluation for future:

–

Final decision depends on costs/benefits

(47)

47

Sl eep Transi stors Reduce Leakage

Power

70

Mbit

SRAM IR photos

>3x SRAM leakage

reduction with use of

sleep transistors

Normal SRAM

sub

-

block leakage

Sleep transistors

shut off leakage in

inactive sub

-

blocks

Power

Saving

Feature

V

SS

V

DD

NMOS

Sleep

Transistor

(48)

48

87 mm

2

83 mm

2

Die size

21 W

24.5 W

Thermal design power

2 MB

1 MB

L2 cache

140 million

77 million

Transistors

2.1 GHz

1.7 GHz

Frequency

90 nm

(Dothan)

130 nm

(Banias)

Pentium

®

M processor

Si l i con Scal i ng Conti nues to Improve

Densi ty, Performance, Power, Cost

Mobi l e CPUs

The power

challenge

(49)

49

Sl eep Transi stors

Reduce ALU Leakage

Scan

FIFO

Scan

out

Sleep

ALU

Body bias

Control

37X leakage reduction

demonstrated on test chip

Scan

PMOS

PMOS underdrive

underdrive

V

_cc_cc

PMOS overdrive

PMOS overdrive V

V

_ss_ss

Virtual

Virtual V

V

_cc_cc

Virtual

Virtual V

V

_ss_ss

Scan

capture

control

Dynamic

ALU

3232

NMOS overdrive

NMOS overdrive V

V

cc_cc

NMOS

NMOS underdrive

underdrive

V

_ss_ss

ALU core

3

3-

-bit A/D

bit A/D

ALU

Body

Bias

PMOS

Sleep

Body

Bias

V

ss

external

V

cc

external

Sleep transistor

and body bias

control

Sleep transistors

Source: ISSCC 2003, Paper 6.1

(50)

50

Advances i n Power Effi ci ent Desi gn

0

50

100

150

200

250

300

350

Cache Switch

Cache Igate

Cache Ioff

Core Switch

Core Igate

Core Ioff

IO bias

DCAP lkg

Using

prior

design

techniques

With new

power

reduction

techniques

From ISSCC 2005

Paper 10.1

“

The Implementation of

a 2

-

core Multi

-

Threaded

Itanium

TM

Family

Processor

”

Power

(W)

(51)

51

1.72 Billion

transistors

21.5 mm

27.72 mm

Business Critical Features

1MB L2I

2-Way

Multi-Threading

Foxton

Power

Controller

2 X 12MB L3

Caches with

Pellston

Soft Error Detection

and Correction

Dual

(52)

52

Si l i con Scal i ng Conti nues to Improve

Densi ty, Performance, Power, Cost

Server CPUs

130 nm 90 nm

Madison

Montecito

Cores/Threads

1/1

2/4

Transistors

0.41

1.72

Billion

L3 Cache

6

24

MByte

Frequency

1.5

>1.7

GHz

Relative Performance

1

>1.5x

Thermal Design Power

130

~100

Watt

The power

challenge

(53)

53

Dual Core

Core

Cache

Core

Cache

Core

Voltage = 1

Freq = 1

Power = 1

Perf

= 1

Voltage = -15%

Freq = -15%

Power = 1

Perf

= ~1.8

The power challenge

(54)

54

Mul ti

-

Core

C1

C2

C3

C4

Cache

Large Core

Cache

1

2

3

4

1

2

Small

Core

1

2

3

4

1

2

3

4

Power

Performance

Power = 1/4

Performance = 1/2

Multi

-

Core:

Power efficient

Better power and

thermal management

(55)

55

Performance and Power Effi ci ency

Increase wi th Paral l el Archi tecture

FORECAST

DUAL/MULTI

-

CORE

2000

2008+

Relative

processor

performance*

(constant

power

envelope)

2004

SINGLE

-

CORE

10X

*Average of SPECInt2000 and SPECFP2000 rates for Intel desktop

*Average of SPECInt2000 and SPECFP2000 rates for Intel desktop processors

processors

vs

initial Intel

®®

Pentium

®®

4 Processor

Source: Intel

3X

The power

challenge

(56)

56

Agenda

y

Moore

’

s Law and scaling

y

The power challenge

y

(57)

57

Future Hi gh

-

k Di el ectri c

Wi l l Reduce Gate Leakage

Silicon substrate

Gate

3.0nm High-k

Silicon substrate

1.2nm SiO

2

Gate

L

ower

power

> 100x reduction

Gate dielectric

leakage

Faster transistors

60% greater

Gate capacitance

Benefit

High

-

k vs. SiO

2

Fo

r F

utu

re

Im

ple

me

nta

tio

n

Fo

r F

utu

re

Im

ple

me

nta

(58)

58

Gate Di el ectri c Scal i ng (Hi gh

-

K)

1

10

1990

1995

2000

2005

Gate Dielectric

Thickness

(nm)

1

10

1.2 nm

Thinner equivalent gate oxide increases transistor performance

90nm

.13um

.18um

.25um

.35um

Generation

2010

K=

3

X

K

D

K=

5

X

K

(59)

59

Conti nuati on of Moore

’

s Law

Strained

Si

Strained Si

Strained

Si

Strained

Si

Strained

Si

Channel

P1270

P1268

P1266

P1264

P1262

Px60

P858

P856

Process Name

300

200/300

200

Wafer Size (mm)

Metal

Poly

-

-silicon

silicon

Poly

-

-silicon

silicon

Poly

-

-silicon

silicon

Poly

-

-silicon

silicon

Poly

-

-silicon

silicon

Gate electrode

High

-

k

High

-

k

High

-

k

SiO

2

SiO

2

SiO

2

SiO

2

SiO

2

Gate dielectric

?

Cu

Al

Inter

-

connect

22 nm

32 nm

45 nm

65 nm

90 nm

0.13

µm

µ

m

0.18

µm

µ

m

0.25

µm

µ

m

Process

Generation

2011

2009

2007

2005

2003

2001

1999

1997

1st Production

Potential candidate for introduction

Subject to change

Intel found a solution for

High-k

and metal gate

Intel found a solution for

High

-

k

and metal gate

(60)

60

y

Structures measured in nanometers

–

Less than 0.1

-

micron (100nm)

y

New processes, materials, device structures

–

Incrementally changing silicon technology base

y

Materials manipulated on atomic scale

–

In one or more dimensions

y

Increasing use of self

-

assembly

–

Using chemical properties to form structures

Nanotechnology innovations will extend

silicon technology and Moore

’

s Law

Nanotechnol ogy Hal l marks

(61)

61

BOX

Source

Drain Source

Gate

Drain Si fin - Body!

FinFET

Surroundi ng the Semi conductor

Drain

Source

Metal

Gate Insulator

Source

Drain

Gate

(62)

62

Tri-Gate

Planar CMOS

Tri-gate Transistor works in

Three Dimensions

Gate 2

Gate 3

Gate 1

Buried Oxide

Gate

SiO

2

SiO

2

(63)

63

Si

T

Si

L

g

Si

T

Planar fully depleted SOI

Double-gate (e.g. FINFET)

W

Si

L

g

T

Si

Isolation

(Non-Planar)

(Planar)

W

Si

L

g

T

Si

Tri-gate

(Non-Planar)

Most

Manufacturable

New Devi ce Archi tecture

Tri

(64)

64

Tri

-

Gate Transi stor:

“

A templ ate for the future

”

SOURCE

DRAIN

GATE

Technical details presented at:

ISSDM Conference, Japan, Sept 17, 2002

Source: Intel

SOURCE

DRAIN

(65)

65

Nano

-

Devi ce Structure Evol uti on

Tri-gate Transistor

Gate

Fully-Surround Gate

Transistor

Best Electrostatics

and Scalability

Improved

Electrostatics

SiO2

Gate

SiO2

Conventional Planar Transistor

(66)

66

5 nm Si

Nanowire

Metal Gate

2.0 nm

High-K

Semi conductor Nanowi res

Chemically synthesized

silicon nanowires with

diameters <20nm (not

defined by lithography).

Si Nanowire

(67)

67

Carbon Nanotube Tutori al

y

Rolled

-

up graphene sheet(s)

y

Roll

-

up vector determines

electronic properties of tubes

–

metallic

–

semiconducting

y

Dimensions:

1

-

25nm depending on how they

are form.

Semi-conductor

Metal

R

r

(68)

68

Carbon Nanotube Transi stor

Source

Carbon

Nanotube

-D = 1.4 nm

Gate

Drain

L

g

= 75 nm

Chemically synthesized

semiconducting

nanotubes with

diameter=2nm

form the transistor

channel.

(69)

69

Energy

-

del ay product for PMOS

(70)

70

Compound Semi conductor (

l l l

-

V)

Transi stors

Gate

Drain

Source

Multi

epitaxial

layers

Research transistor based

on multi-epitaxial layer

structure in compound

semiconductors.

So u r ce : I n t e l

(71)

71

III/V is a 2015 Transistor option

•

3x faster or 10x lower power

•

Integration with silicon key

CMOS to conti nue for 15

-

20 years or more;

Moore

’

s Law coul d be extended i ndefi ni tel y vi a new

archi tectures, heterogeneous i ntegrati on, 3D

0.2um InSb

0.2um NMOS

Po

w

e

r

C

o

nsum

pt

io

n

0.2um InSb

0.2um NMOS

T

ra

n

si

st

o

r

Sp

e

d

(72)

72

Energy

-

del ay product for NMOS

(73)

73

Transistor Scaling

& Roadmap

LG= 10nm

20nm Length

(Development)

25 nm

15nm

15nm Length

(Research)

65nm Node

P1264

2005

45nm Node

P1266

2007

90nm Node

2003

32nm Node

P1268

2009

22nm Node

P1270

2011

10nm Length

(Research)

C

-

nanotube

Prototype

(Research)

Nanowire

Prototype

(Research)

5 n m 5 n m

(74)

74

Moore

’

s Law Today

Moore’s Law

y

Moore

’

s Law = Doubling of

components at fixed intervals while

reducing production

cost/component

y

Moore's Law is alive and well

y

CMOS has been an important

enabler of Moore

’

s Law

y

Moore's Law may go on indefinitely,

and extend beyond traditional CMOS

y

“

End of CMOS Scaling

”

≠

“

End of

Moore

(75)

75

Bipolar

Moore

’