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Gordon Moore ISSCC 021003

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(1)

NO EXPONENTIAL IS FOREVER . . .

NO EXPONENTIAL IS FOREVER . . .

(2)

Worldwide Semiconductor Revenues Worldwide Semiconductor Revenues

$B

$B

1 10 100 1000

'68 ’70 '72 '74 '76 '78 '80 '82 '84 '86 '88 ’90 '92 '94 '96 '98 '00 '02'02

1 10 100 1000

'68 ’70 '72 '74 '76 '78 '80 '82 '84 '86 '88 ’90 '92 '94 '96 '98 '00

(3)

Transistors Shipped Per Year Transistors Shipped Per Year

1017

1016

1015

1014

1013

1012

1011

1010

109

Units

1018

'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02

(4)

Average Transistor Price By Year Average Transistor Price By Year

$

$

10

1

0.1

0.01

0.001

0.0001

0.00001

0.000001

0.0000001

'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02

(5)
(6)
(7)
(8)

Integrated Circuit Complexity Integrated Circuit Complexity Transistors

Transistors

Per Die

Per Die

Source: Intel Source: Intel

1965 Actual Data

1965 Actual Data

1960

1960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

(9)

Integrated Circuit Complexity Integrated Circuit Complexity

MOS Arrays MOS Logic 1975 Actual Data

Per Die

Per Die

1965 Actual Data

1965 Actual Data 109

1975 Projection

1975 Projection 108

Source: Intel Source: Intel

1960

(10)

Integrated Circuit Complexity Integrated Circuit Complexity

1K

80286 i386™i386™

i486™

i486™

Pentium

PentiumPentiumPentium®® ®

256M 512M512M

Pentium

Per Die

Per Die

1965 Actual Data

1965 Actual Data 109

Source: Intel Source: Intel

„

„ MMemoryemory

1975 Projection

1975 Projection 108

107

S

S MicroprocessorMicroprocessor

106

(11)
(12)

Projected 2000 Wafer, circa 1975 Projected 2000 Wafer, circa 1975

57

"

(13)

90 nm Generation Interconnects 90 nm Generation Interconnects

M7

M6

M5

M4 M3 M2 M1 Low-k CDO

Dielectric

Copper Interconnects

(14)

Minimum Feature Size Minimum Feature Size

'90 '95 ’00 '05 '10

Intel [update 5/20/02]

ITRS [2001 edition] **

Feature Size

Feature Size

(microns)

** Planar Transistor; remaining data points are ICs.

** Planar Transistor; remaining data points are ICs.

Source: Intel, post ‘96 trend data provided by SIA

Source: Intel, post ‘96 trend data provided by SIA

International Technology Roadmap for Semiconductors (ITRS)

International Technology Roadmap for Semiconductors (ITRS)

^ [ITRS DRAM Half

(15)

1

1 µµmm22 SRAM CellSRAM Cell

P501 Contact

P501 Contact

1978

1978

P1262 SRAM Cell

P1262 SRAM Cell

2002

2002

P501 Contact

P501 Contact

1978

1978

P1262 SRAM Cell

P1262 SRAM Cell

2002

2002

1

(16)

50nm Resist Lines With 193nm Light 50nm Resist Lines With 193nm Light

--0.2um focus0.2um focus --0.3um focus0.3um focus

“best focusbest focus””

+0.2um focus

(17)
(18)

Minimum Insulator Thickness vs Time Minimum Insulator Thickness vs Time

1 10 100

'69 '72 '75 '78 '90 '93 '96 '99 '02 '05

Oxide Thickness

Oxide Thickness

(Nanometers)

Source: Intel

(19)

High K for Gate Dielectrics High K for Gate Dielectrics

Silicon substrate

Silicon substrate

Gate

Gate

3.0nm High

3.0nm High--kk

Silicon substrate

Silicon substrate

1.2nm SiO

1.2nm SiO22

Gate

Gate

Experimental high-k 1.6X

< 0.01X 90nm process

1X 1X Capacitance

Leakage

Source: Intel

(20)

Processor Performance (MIPS) Processor Performance (MIPS)

0.01

1970 1975 1980 1985 1990 1995 2000 2005

MIPS 386

8008

8080

286

Pentium® Pentium® 2

8086

4004

486

(21)

Processor Power (Watts)

Processor Power (Watts) -- Active & Leakage Active & Leakage

0.001 0.01 0.1 1 10 100 1000

1960 1970 1980 1990 2000 2010

Po

w

e

r (

W

) ActiveActive

Leakage

(22)

Processor Supply Voltage Processor Supply Voltage

1 10 100

1970 1980 1990 2000 2010

Power

Suppl

y

(

V

ol

(23)

New Materials and Device Structures New Materials and Device Structures

Extending Transistor Scaling Extending Transistor Scaling

(24)

Tri

Tri--Gate Transistor StructureGate Transistor Structure

Current

Lg

Source

Drain

Gate

Tox

SiO2

HSi

(25)

Technology Generations to Come Technology Generations to Come

Double the Density

Double the Density

Reduce Line Width by 0.7x

Reduce Line Width by 0.7x

130nm

130nm¼¼90nm90nm¼¼60nm60nm¼¼45nm45nm¼¼30nm30nm¼¼??

2 or 3 years between generations

2 or 3 years between generations

~10

(26)

EUV Printed and Etched Lines EUV Printed and Etched Lines

(27)
(28)

Lithography Tool Cost ( $ ) Lithography Tool Cost ( $ )

Exp+04

Exp+04

Exp+05

Exp+05

Exp+06

Exp+06

Exp+07

Exp+07

Exp+08

Exp+08

1960

1960 19701970 19801980 19901990 20002000 20102010

Litho Tool Cost ( $ )

(29)

NO EXPONENTIAL IS FOREVER . . .

NO EXPONENTIAL IS FOREVER . . .

BUT

BUT

WE CAN DELAY “FOREVER”

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