Silicon Integration
for Convergence
Sunlin Chou
Senior Vice President General Manager
Technology and Manufacturing Group
2
Silicon Integration for Convergence: Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
Silicon Integration for Convergence: Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
4
Computing + Communications Vision: Data Anytime, Anywhere
@ the Office
@ the Office 10/100/GbE10/100/GbE
@ Home
@ Home
Everywhere
Everywhere
Else
Else
Broadband Broadband Cellular: Voice + Data
Cellular: Voice + Data
802.11b/a
802.11b/a
@ Hotspots
@ Hotspots
802.11b/a
802.11b/a
10/100
10/100 802.11b/a802.11b/a
Cellular
Memory
Memory
Converged
Converged
Computing and
Computing and
Communications
Communications
Microprocessors
Microprocessors
Silicon is the Engine
Drive convergence with silicon integration
Drive convergence
Drive convergence
with silicon integration
6
Silicon Scaling and Integration
Improve Performance, Power, Cost
Relative scale (log)
Relative scale (log)
1993
1993 19951995 19971997 19991999 20012001 20032003 20052005
.5µm .35µm .25µm .18µm .13µm 90nm 65nm
1
Scaling effects on transistors Scaling effects on transistors
Silicon scaling Silicon scaling
Source: Intel
Cell Phones For Voice + Data
Flash Memory Density Growth in Japan
Flash Memory Density Growth in Japan
Mb
0 40 80 120 160 200
1998 1999 2000 2001 2002
VOICE ONLY
VOICE ONLY PACKETIZED DATAPACKETIZED DATA 256 COLOR256 COLOR 4K COLOR4K COLOR JAVA APPS. JAVA APPS.
44K COLOR 44K COLOR RICH JAVA APPS. RICH JAVA APPS.
MP3 MP3 PHOTOS PHOTOS
Convergence increases silicon usage
Convergence increases silicon usage
8
Converged Cell Phone
Integration Opportunities
Radio (RF) Radio (RF)
Signal Signal Processing Processing
Rx
Radio (RF)
Radio (RF)
Signal
Signal
Processing
Processing
Rx
Communications ComputingComputing MemoryMemory
CMOS (Digital, Analog)
CMOS (Digital, Analog)
GaAs
GaAs//SiGeSiGe (for RF)(for RF)
CMOS (Digital)
2 Die
2 Die
1.4mm Package Height
1.4mm Package Height
4 to 5 Die
Under Research
Under Research
8 Die Stack
8 Die Stack
50
Integration via Packaging
Ultrathin
Ultrathin Stacked Stacked Chip Scale Packaging Chip Scale Packaging
10
Wireless Internet on a Chip by Flash+Logic Integration
Power mgmt & peripherals 90nm Transistor Gate
on 0.13µm Process
90nm
Logic Logic
0.16µm2 Flash Cell
Flash Flash
PXA800F Cellular Processor
PXA800F Cellular Processor
Cell
Intel® MicroSignal Arc
h
itecture
Integration improves density, speed, power consumption
Integration improves density,
Integration improves density,
speed, power consumption
speed, power consumption
Source: Intel
Silicon Integration for Convergence: Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
12
Intel’s Technologies for Convergence: CMOS Base + Apps-Specific Modules
Integrated PCA
Integrated PCA
(Cellular)
(Cellular)
Processor
Processor
Logic CMOS Base
Logic
Logic
CMOS Base
CMOS Base
Flash Memory
Flash Memory
Flash Memory MemoryMemory
Flash + Logic + Analog
Flash + Logic
Flash + Logic
+ Analog
+ Analog
Mixed Signal
Mixed Signal
Mixed Signal Ethernet/Ethernet/WiFiWiFi
High Frequency
Logic
High
High
Frequency
Frequency
Logic
Logic OpticalOptical
Economy of scale (shared base) + application-specific optimization
Economy of scale (shared base)
Economy of scale (shared base)
+ application
Process Modules Available for
Ethernet/WiFi and Optical Comm
M6 VIA Inductor Spiral
Inductor Spiral
M7
M6 BOTTOM PLATE MIM CAP
MIM RES
MIM Capacitor/Resistor
MIM Capacitor/Resistor
STI
COLLECTOR
EMITTER
CMOS
CMOS Poly Poly SiSi ResistorResistor SiGe
SiGe BJTBJT
S D
POLY Si
14
10Gb/s SONET Transceiver on 90nm Technology
RX TX
Output @ 10.66Gb/s
Single chip CMOS Single chip CMOS
Precision passives Precision passives
(R, L, C) (R, L, C)
Source: Intel
802.11 (WiFi) Integration Improves Cost and Power
Today
Today 90nm90nm
MAC
MAC BasebandBaseband
RF Radio
RF Radio
Digital Functions
Digital Functions
Analog Functions
Analog Functions
Analog
Analog
Front End
16
Radio Research at Intel
Silicon Radio Silicon
Silicon
Radio
Smart Antenna Systems
Smart Antenna
Smart Antenna
Systems
MEMS: Micro Electro Mechanical Systems
MEMS Antenna Switches and Filters for Multi Band Radios
Transmit
Transmit
Receive
Receive
MEMS Antenna Switch
MEMS Antenna Switch
MEMS Filters
MEMS Filters
Antenna
Antenna
MEMS benefits: Low insertion loss + component integration
MEMS benefits: Low insertion loss
MEMS benefits: Low insertion loss
+ component integration
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Integrated MEMS RF Switches
Gate Gate
Source Source Drain
Drain
Switch design
Switch design
Multiple gold RF switches integrated
Multiple gold RF switches integrated
into one silicon MEMS chip
into one silicon MEMS chip
Fabricated using
silicon processing technology
Fabricated using
Fabricated using
silicon processing technology
silicon processing technology
Source: Intel
MEMS Integrated with CMOS
MEMS MEMS Varactor Varactor
20
Silicon Integration for Convergence: Three Strategic Combinations
y Computing + Communications
y CMOS Base + Application Specific Modules
Silicon Devices Shrink to Virus Size..
50nm
50nm 100nm100nm
Influenza virus
Influenza virus
Source: CDC
Transistor for
Transistor for
90nm Process
90nm Process
Source: Intel
Source: CDC
Source: Intel
..and Nanotechnology Scale
22
Intel in Production with
Nanotechnology (< 100nm)
10000
Micron NanoNanometermeter-
-1970 1980 1990 2000 2010 2020
Nominal feature size Nominal feature size
Nanotechnology
Gate Length
Gate Length
Source: Intel
Lithography is the Designer’s “Brush”
Lithography is indispensable for defining locations/configurations
of circuit elements/functions
Lithography is indispensable for
Lithography is indispensable for
defining locations/configurations
defining locations/configurations
of circuit elements/functions
24
Lithography Gap to Close with EUVL (Extreme Ultra Violet Lithography)
Initial Production
Initial Production
1000 Feature size
Feature size
157nm
157nm
13nm (EUVL)
13nm (EUVL)
Lithography
Lithography
Wavelength
Source: Intel
26
Full Field Images Produced by EUV Prototype Exposure Tool
100nm contacts 1:1
100nm contacts 1:1
80nm elbows 1:1
80nm elbows 1:1
24 x 32.5mm
24 x 32.5mm2 2 field field
200mm wafer
200mm wafer
Commercial EUVL exposure tool feasibility demonstrated
Commercial EUVL exposure tool
Commercial EUVL exposure tool
feasibility demonstrated
feasibility demonstrated
Source:
EUV Masks Simpler to Pattern and Inspect than Optical Masks
Est. Cost/Layer:
Est. Cost/Layer:
< $90K
< $90K
EUV Mask EUV Mask
(45nm Process)
(45nm Process)
Est. Cost/layer:
Est. Cost/layer:
$100K (OPC Only)
$100K (OPC Only)
$150K (OPC + Comp)
$150K (OPC + Comp) Optical Mask Optical Mask
(45nm Process)
(45nm Process)
EUVL masks will cost less than optical lithography masks
EUVL masks will cost less than
EUVL masks will cost less than
optical lithography masks
28
EUVL Being Developed and Commercialized Worldwide
Japan
Japan
> 10 Companies
> 10 Companies
Consortia:
• MIRAIMIRAI
Europe
Europe
> 50 Companies
> 50 Companies
Consortia:
Consortia:
•
• PREUVEPREUVE •
• MEDEA+MEDEA+ •
> 40 Companies
> 40 Companies
Intel’s Transistor Research in Deep Nanotechnology Space
Experimental transistors for future process generations
Experimental transistors for future process generations
30nm 65nm process
65nm process
2005 production
2005 production 45nm process45nm process 2007 production
2007 production 32nm process32nm process 2009 production
2009 production 22nm process22nm process
2011 production
2011 production
Transistors will be improved for production
Transistors will be improved
Transistors will be improved
for production
30
Intel’s Transistors Run Fast on 90nm Strained Silicon Process
Normal Silicon Lattice Strained Silicon Lattice Normal Silicon Lattice Strained Silicon Lattice
Current Flow
Current Flow
Normal
Normal
electron
electron
flow
flow
Faster
Faster
electron
electron
flow
flow
Source: Intel
Source: Intel
A new way to speed up with nanotechnology
A new way to speed up
A new way to speed up
with nanotechnology
Transistors Improved by Going 3-D
Intel’s experimental Tri
Intel’s experimental Tri--gate transistorgate transistor raises performance, lowers off current raises performance, lowers off current
Gate
Gate
Silicon
Silicon
Drain
Drain
Source
Source
Gate Gate
Source Source
Drain Drain
New nanotechnology device options coming
New nanotechnology
New nanotechnology
device options coming
32
Future Nanotechnology will Ride on Silicon Technology Base
Silicon
Silicon
Silicon
Nanowire
Nanowire**
Nanotube
Nanotube//NanowireNanowire Transistors
Transistors
Carbon
Carbon
Nanotube
Innovations expected to overcome scaling limits
*Source: Morales &
*Source: Morales & LieberLieber, Harvard , Harvard UnivUniv
Innovations expected to overcome scaling limits
Nanotechnology Brings Welcomed Opportunities
y Renewal and extension of silicon technology
– New materials, processes and device structures
– Integrate innovations into silicon technology base
– Break limits of “static” silicon scaling model
y Intel plans to lead in nanotechnology
– Already in production with nanotechnology
– Heavily engaged in nanotechnology R&D
34
Video
Nanotechnology extends Silicon Technology
Nanotechnology extends Silicon Technology
Dr. R. Stanley Williams
Dr. R. Stanley Williams
HPL Fellow, Director, Quantum Science Research
HPL Fellow, Director, Quantum Science Research
Hewlett
Hewlett--Packard LabsPackard Labs
Professor Yoshio Nishi
Professor Yoshio Nishi
Professor Electrical Engineering
Professor Electrical Engineering
Director, Stanford
Silicon Integration for Convergence: Three Strategic Combinations
y Computing + Communications
– Use silicon scaling and integration to improve performance, energy efficiency, cost
y CMOS Base + Application Specific Modules
– Shared CMOS base for economy of scale
– Process modules optimized for each application
y Silicon Technology Base + Nanotechnology
– Nanotechnology innovations will ride on silicon