A Built-In Self-Test (BIST) Technique for Single-Event Transient Testing in Digital Circuits

As the minimum dimensions of the integrated circuits (ICs) continue to decrease to provide high-density, high-performance circuits, their susceptibility to SETs has also increased significantly [3]-[15]. In addition, perturbed error rates caused by SETs are a strong function of the SET pulse width, the arrival time of a SET with respect to the clock edge, and the clock frequency [11][16]. This is because for a SET to be captured by a lock, a SET is required to arrive within the setup and hold time requirements of the lock [3].

It also depends on the properties of the semiconductor material such as doping and junction depth. This causes a distinct difference in the shape of the current pulse from previously observed technologies. 2, which is critical in determining the width of the SET that propagates through the circuit [45].

The number of combined logic errors due to SETs is largely dependent on the pulse width and arrival time of the SET pulse with respect to the clock edge [43], [44]. Characteristics of a SET, such as its width, arrival time relative to the clock edge, amplitude, and states of the gates it passes through, determine whether a SET will actually reach its destination and cause an error. If an ion attack occurs on the drain of the inverter farthest from the latch, the SET will propagate to the next inverter.

In addition to the amplitude and duration of a SET pulse, which are key factors that determine the soft error rate, the clock frequency and the arrival time of the SET pulse at the clock edge are also crucial factors that affect the soft error rate.

Fig. 1. Typical shape of the SE charge collection current at a junction

Delay chain (delay = ∆t)

Since the latch consists of two interconnected NAND gates, the latch delay can be approximately equal to 4 gates. The value of ∆t is the sum of the delay time in the 'in' signal and the delay of the latch as shown in figure. When Q goes high, a pulse is produced at the output of the XOR gate, the width of which depends on the delay set by 'delay element 2'.

By using different lengths and types of delay chains, the width and offset of the pulse with respect to the clock can be varied. The maximum length of the sequence before the PRNG starts repeating is determined by the size of the seed state, measured in bits. Therefore, if the seed state of a PRNG contains n bits, the maximum length of the random sequence that can be produced is 2n.

Moreover, the randomness of the numbers produced can be easily varied by using a more complex LFSR [61]-[65]. By using such PRNGs in combination with delay elements to control both the width and arrival time of the pulse, pulses can be randomly generated with varying arrival times and delays. Simulation and experimental results for the Pulse-Generate circuit are presented in this section, verifying the practicality of the built-in test design scheme.

The low-current inverters required an analog control input to control the delay through the inverter chain, and varying this control voltage changed the width and arrival of the pulse relative to the clock. The pulse width is plotted as a function of the control voltage of the low current inverter in figure. The red oval in the layout shows the location of the Pulse-Generate circuit in the fabricated IC.

The Pulse-Capture circuit captures a SET pulse in a series of latches, which are then read out to determine the width of the pulse. For the measurement of the pulse widths generated from the Pulse-Generating circuit, its output was fed into the input of the Pulse-Capture circuit. The range of pulse widths measured for varying control voltages of the current-starved converters is shown in Fig.

Fig. 8. Technique to control transient onset w.r.t to a synchronous input.

Control Voltage (V)

Whenever a pulse was generated, it triggered the Pulse-Capture circuit which measured the pulse width in terms of inverter delays. The pulse width recorded with the pulse capture circuit varied from about 450 ps to over 4 ns. The propagation delay for each measurement stage (latch) in the Pulse-Capture circuit at 180 nm technology was 150 ps.

Simulations indicated that when transients propagated through a long chain of gates, they were less than about two to three times the propagation delay of a single step.

Pulse width (ns) pulse width based onlatch delay

The output of the pulse capture function may show the pulse width as one, two, or three delays, although this may not be the actual initial pulse width. instead, it may be the width of the attenuated pulse. The output of the Pulse-Generate circuit was connected to the output board and also measured with an oscilloscope. The ringing seen in waveforms can be caused by impedance mismatches, cables used for testing, and stray capacitance of the measurement system.

Wrist arrives near the falling edge of the watch. get closer to the rising edge of the clock. arrives near the falling edge of the clock, and is mainly present in the negative half of the clock cycle. Charge collection in combinational logic is different from that in sequential logic. sequential logic, there is feedback in which a voltage transition generated at the drain of an off transistor feeds back to the gate of the same transistor and to the gate of its complementary transistor. The gates of the nmos and pmos are connected together, forming the input to the inverter.

The drains of the two transistors are short-circuited, forming the output of the inverter. When the input is a logic low, nmos is off, conversely, the drain of the transistor is biased. When a single-event attack occurs at the drain of the nmos, most of the charge generated in or near the junction by the energetic ions will be collected.

With an unchanging bias on the NMOS drain, charge collection persists, unlike the case of sequential logic, where the collected charge is removed. Previous research [69] has also shown that more than 80% of the combinational soft errors in a circuit are caused by less than 50% of the nodes. This also allows a reduction in the total number of nodes to be tested in a BIST approach.

SETs are a cause for concern and change the computational functionality of the circuit only when captured by the storage elements in the circuit. Propagation of the transition to the output depends on the following masking factors a) logical masking occurs if there is no active path from the sensitive node to the output or a latch;. In order to identify the insertion nodes, single event simulations were performed on each node of the circuit.

Fig. 17. Pulse arriving close to the rising edge of the clock

Node

Total errors from all nodes 300

Errors covered (80 percent) by 16 nodes

A single-event shot at each of nodes 1,2,3, and 4 can be modeled by a single-event shot at only node 4. The BIST was then used to inject fault pulses into the 16 nodes selected to give an overall assessment of the county's vulnerability to single events. To calculate the response of all 300 nodes, the 16 input nodes were injected with impulses several times, and this accounted for about 80% of the total disturbances, as shown in Fig.

The dashed yellow and blue bars overlapping the red bars account for 80% of the errors accounted for by the selected 16 nodes. Single-event attacks (both n-hits and p-hits) were simulated at each node of the circuit, for all 256 input combinations, resulting in a total of approximately 83,000 simulations. Using this analysis, the number of insertion nodes that contributed to the majority of the errors was determined to be 11 nodes.

Using BIST to inject error pulses into these selected nodes covered approx. 88% of the total recorded errors generated using the exhaustive approach. The bars shown in blue are the errors covered by the selected 11 nodes of the 4-bit multiplier circuit. It can be seen that most of the blue bars overlap the red bars, showing that they cover a large percentage of errors recorded from all 211 nodes.

The figure shows a multiplexer with an unchanged node logic, low-pass or high-pass that can be entered into the circuit and mode. The pulse generator circuit, which is part of the BIST mechanism, was simulated and fabricated in the 180 nm technology node. The width and offset of the pulse can be varied by using different types of delay elements.

To make the BIST design more efficient and realistic, identifying receptive nodes and exploiting masking factors reduce the total number of nodes that require pulse injection. By monitoring the outputs of the circuit during operation under the BIST mechanism, the total number of errors can be recorded. Schneiderwind, “Dependence of the SEU window of logic circuit vulnerability on the size of the delayed charge,” IEEE Trans.

Tront, “HDL simulation of the effects of single event disturbances on microprocessor program flow”, IEEE Trans. Michael, “An Embedded Self-Test Scheme for VLSI,” in Design Automation Conference, Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95, p.