CHAPTER I

The InAs - AlSb HEMT derives its high-speed performance from the inherent fast electron transport properties of the channel semiconductor. The most prominent problem in the initial stages was the extreme reactivity of AlSb in air.

Fig. 1.a) The DC output characteristics of a vertically scaled 100 nm gate length InAs - AISb HEMT

Band Structure and Hole Removal

The absence of the Schottky gate eliminates the band-upward slope of the upper AlSb layer in the access regions. For the standard Au/TiW or Cr/Au gate metallization, the band bending in the top AlSb layer is quite large, which creates a favorable situation.

Figure 9. Vertical cross-section of InAs - AlSb HEMTs. b) Vertical band diagram underneath gate (solid line) and in the access regions (dashed line)

DC Transconductance and V th Comparison for Different Source-Drain Spacing

For Vgs = -0.4 V, the effect is strongly seen at drain voltages greater than Vg - Vde in devices with shorter gate length (Fig. 12). The short gate length devices show significantly increased going for drain voltages greater than Vg - Vde.

Figure 10. DC transconductance for 4 HEMTs with gate lengths of 100 nm, 250 nm, 500 nm and 700 nm and S/D spacing = 2 m

Avalanche History in RF Transconductance

The flattening of the RF gm curves for both devices around the peak is partly due to this, in addition to the effects of Cgd and Cgs. The shift in Vgs corresponding to the peak avalanche condition during high-frequency switching results in a slight shift in the gm peak for both devices.

Figure 16. Simulated a) DC transconductance for devices with 100 nm gate length and S/D spacings 2 and 4 m, with ac g m = I d,ac / V g,ac , for a 25 GHz, 25 mV p-p signal, for the b) 2 m and c) 4 m S-D device

Characteristics of Devices Used in Stress Experiments

The devices with simultaneously low threshold voltage and gate current had a starting threshold voltage of approximately -0.6 V and a gate current at the highest negative gate voltage (Vgs = -0.8 V) and Vds = 0 that was less than 0.1% of the drain current was at Vgs = 0 and Vds = 0.5 V. Since most good devices pinched off at ~ -0.7 V, we took the DC threshold voltage as an indication of the strength of the vertical field in the channel at the selected prestress condition. While incomplete pinch-off devices exhibit source-to-drain current at high Vds near or below the threshold voltage, in the high gate leakage devices the drain current flows from gate to drain at similar gate biases, rather than to the source.

Fig. 17. High and low negative threshold voltage devices – both with 100 nm gate length

Bias Corresponding to Maximum Hot Carrier Condition

This is due to the low hole mobility of InAs, AlSb or In0.5Al0.5As compared to the electron mobility in InAs. The hole created by impact ionization in the InAs channel has an energy that is a significant fraction of the electron energy in the InAs channel—before it gains additional energy from electric fields or band gaps). Since devices are most prone to breakdown near the impact ionization peak (as opposed to large deviation or gate bias), this is a strong indication that the observed breakdown is driven by hot carriers.

Figure 19. I g -V g characteristics of a 2  20 m HEMT, for V ds = 0 to 0.4 V, in steps of 0.1 V

Degradation – Threshold Voltage and Transconductance Peak Shift

Thus, for the same bias conditions, the device with larger Vg - Vth has a lower electric field in the channel. As the gate current evolves as defects are turned on or off, the fields are modified by changes in the charge states of the defects. Since the threshold voltage is shifted negative, an effective increase in the amount of positive charge on the gate stack occurs with stress.

Figure 21. (Top) Degradation in peak g m and shift in threshold voltage (V ds = 0.4 V) under 5 hours of stress at V gs = -0.5 V, V ds = 0.4 V, and g m plots of a 2  20 m wide HEMT with 100 nm gate

Room Temperature Annealing of Stressed Devices

The recovery rates are quite similar with 50% recovery achieved in 6-8 hours and over 90% recovery achieved in 2 days. This may indicate that more than one type of defect is responsible for the degradation of the device. While a simple extrapolation of the trends near full recovery suggests that longer annealing will lead to super-recovery of the device (introducing a threshold voltage shift to a less negative value than the bias threshold voltage), measurements after two weeks of annealing showed no signs . of super recovery.

Figure 30. Fractional recovery of V gm, peak of three devices with varying degrees of initial degradation

Location and Metastable Nature of Defect

The greater degradation at high fields in the channel indicates the role of hot carriers in the degradation process. Although it is unlikely that hot electrons will retain sufficient energy in the AlSb away from the interface (given the high Ec = 1.3 eV), a sufficiently large number of energetic holes (derived from avalanches in the channel) exist at the tension biases (Fig. 31). a) Electron temperatures in bias conditions at the gate-drain edge in the InAs channel, as shown in figure b) Holes generated by impact ionization gain more energy as they move along the AlSb buffer, away from the channel.

Figure 31. (a) Electron temperatures at bias condition at the gate-drain edge in the InAs channel, as shown in Fig

Native Defects

Oxygen Based Defects

Transition from /-CCBDX to either of the 2 defects at Ef ~ 0.4 eV will change the defect charge state from -1 to +1 or 0, causing a left shift in the threshold voltage. The gray band shows the range of the average of the 2 quasi Fermi levels for the entire operating range of the device. The gray band shows the range over which the average of the quasi-Fermi levels can vary within the operating range of the device, as calculated from Fig.

Figure 33. Position of the average of electron and hole quasi-Fermi levels (dashed lines) obtained from simulations of a HEMT with V th ~ 0.6 V at V ds = 0.4 V and V gs = 0 (top) and -0.8 V (middle)

High Negative V th Devices and Oxygen Based Defects

The Oi,Al (C3v) and Oi,bb configurations of interstitial oxygen also correspond to the degradation tendencies (Fig. For the range of Ef in AlSb, the higher energy configuration Oi,bb (bb implies bridge bond structure of interstitial similar) to the interstitial oxygen in silicon [40]) is neutral, and is therefore more positive than the -2 state of the most stable Oi,Al(C3v). Transition levels for (bottom) substitutional and (top) interstitial oxygen plotted against the Fermi level limits (Vgs = -0.8 V to 0 V) for 2 devices with Vth = -0.6 V (dotted line) and Vth = -1 V (solid line).

Figure 35. Transition levels for (bottom) substitutional and (top) interstitial oxygen plotted against the Fermi level limits (V gs = -0.8 V to 0 V) for 2 devices with V th = -0.6 V (dotted line) and V th = -1 V (solid line)

Other Impurity Based Defects

For a wide range of Fermi levels, the ground state of TeSb is TeSb(Td)+. Clearly, Te cannot explain the observed degradation, since the metastable DX structures are more negatively charged than the ground state, TeSb (Td)+. Based on the above analysis, among the common intrinsic and extrinsic point defects in such devices, oxygen impurities, both substitutional and interstitial, have long-lived metastable states that are more positive than the ground states.

Origin of Long Lifetime

In the second process, the empty defect level is occupied by an electron thermally excited through the valence band (thermal hole emission). In the third process, the empty state is occupied by an electron moving across the interface. Fermi levels closer to the valence band and thus fewer electrons, the slower recovery under negative gate bias suggests that the defect recovery time depends on the electron density in the upper AlSb layer.

Relative Formation Energies at Growth Conditions

The growth Fermi level in the upper AlSb layer is plotted as a function of the distance from the channel interface. 34, the energies of the formation of both defects during the growth of the upper AlSb layer are plotted. Thus, both defects will be present in much lower concentrations near the channel–upper barrier interface than in the upper parts of the upper AlSb barrier.

Figure 38. Surface Fermi levels during growth for a) bottom AlSb buffer, b) InAs - AlSb top interface and c) top /AlSb barrier

Synopsis of Degradation, Annealing and Comparison with Theoretical Defect Properties

This is consistent with the high channel mobility of the devices both before and after stress, regardless of the magnitude of the threshold shift. This is further supported by the dependence of the annealing times on the applied bias and the slowness of recovery under negative gate bias conditions. The analysis can be considered as part of a general method to assess the importance of a certain defect in the reliability of a device under stress.

Degradation in Small Signal Performance for Devices with Negligible DC Degradation

Devices and Small Signal Measurements

From the measured s-parameters, the Mason short-circuit current gain and one-way power gain were obtained. This is due to two effects: first, Cgd is significant and leads to an additional high-frequency zero in the transfer function. Nevertheless, the frequency dependence of |h21| and U is very close to linear in the high frequency range of the measurement.

Figure 39. Peak f T and f max extracted from |h 21 | and U extracted from s-parameters measured on a 2  20 HEMT with 100 nm gate length and L ds = 2 µm

Device Degradation Under Hot Carrier Stress

The gate bias is relatively small and only a fraction of the bias is dropped vertically across the InAs channel (the rest is dropped across the cap and top and bottom buffer layers). Postvoltage percent change in peak fT (negative sign in % change implies reduction) in HEMTs with gate lengths 250 and 500 nm for S-D spacing 2, 2.5 and 3 m. Since the DC characteristics of the device show almost no degradation, it is unlikely that the frequency-independent components such as Rd, Rs or Rds play a significant role in the small signal degradation.

Fig. 42 shows f T degradation results for 250 and 500 nm gate length devices for S-D spacings of 2, 2.5, and 3.5 m

Modeling Active FET

For this reason, the extraction of equivalent circuit parameters was performed using the externally measured s-parameters. Although this would result in some of the parasitic pad capacitances, pad resistances and inductances being embedded in the active device model extraction, these are unlikely to be important factors in device degradation for two reasons. Second, all these quantities depend on details of the device and the structure of the pad, which is very unlikely to be affected by stress.

Figure 44. The intrinsic equivalent circuit of the HFET [57].

Degradation Mechanism

From Vgs = Vde to ~ -0.3 V, the gate current increases as the impact ionization rate increases, due to an increase in the 2DEG density. Flattening” of the RF gm curve after voltage (similar to comparison between DC and RF in Fig. 45) indicates greater difficulty in removing impact ionization generated holes. In high-frequency operation, the contribution of impact ionization is lost as the generated holes do not keep pace with the rapidly modulating gate signal.

Figure 46. Pre and post-stress RF g m , at 10 GHz. „Flattening” of the RF g m curve post- post-stress (similar to comparison between DC and RF in Fig

Post Stress Increase in Parasitic Capacitances

Parasitic Capacitance Measurement

Extracted capacitances (Cgs and Cgd) before and after voltage at the bias condition for peak fT for a device with gate length 500 nm and S-D distance of 2 microns. 51 shows the extracted capacitances before and after voltage at the bias condition for peak fT for a device with gate length 500 nm and S-D distance of 2 µm. The increase in post-stress gate-to-source capacitance can be explained by the trapping of holes that escape the channel and become trapped at the passivation-cap interface above the source-gate access region.

Figure 51. Extracted capacitances (C gs and C gd ) pre and post-stress at the bias condition of peak f T for a device with gate length 500 nm and S-D spacing of 2 microns

Percent change in peak fT plotted against percent change in (Cgs + Cgd) for devices tested with 2 micron S-D spacing. 52 than for Fig.53 shows that the degradation of gm has a much stronger correlation with the degradation of fT than the increase in parasitic capacitance. The closeness of the points to the line of unity slope (especially for devices with short gate lengths) indicates that the first-order expression of fT holds for high-grade InAs - AlSb HEMTs to a high degree of accuracy.

Figure 53. Percentage change in peak f T plotted vs percentage change in (C gs + C gd ) for the tested devices with 2 micron S-D spacing

High Current Stress and Small Signal Performance

Conclusion

In the cases explained earlier - where the gate current is reduced after stress - the reduction is small - usually no more than 10 - 20. However - the performance improvement under high AC power conditions is very significant and worth an investigation of detailed and complete. Eastman, "The Role of Inefficient Load Modulation in Limiting the Cutoff Frequency of MODFET Current Gain".