Characterization of heavy-ion, neutron and alpha particle-induced single-event transient pulse widths in advanced CMOS technologies

The simulated width of the transients produced by the pulse. circuit for different values of the control voltage agrees well with the experimentally measured transition widths using a pulse. a) Box plot showing mean, ± 1 standard deviation, minimum. and maximum SET pulse width as a function of LET for the 130-nm process. These structures are similar to the arrangement of devices in the respective technologies for which they are used. Box plot of the minimum, average, ±σ and maximum SET pulse widths in the 130-nm process for supply voltages of 1.2 V and 1.1 V.

The width of the SET is also determined by the driving force of the recovering device and by the kinematics of charge collection. Of these, electrical masking and latch window masking depend on the width of the generated SET. Based on the dependence of the SET pulse width on several factors, including the linear energy transfer of the energetic particle and the driving strength of the recovering device, a mathematical model is presented for SET pulse widths in the 90 nm process.

When all of the incident particle's energy is lost, it rests in the semiconductor material. The width of this ion track depends on the energy of the incident ion [Step-88].

Fig. 1.1. SIA roadmap projections for feature size scaling as a function of the year of

Energetic particle strike

Mixed-mode simulations were performed using the exact device dimensions used in the layout of the SET test chips in the 130 nm and 90 nm processes to better understand scaling in SET pulse widths. The SET pulse width is determined by the time at which the recovery drive current overcomes the stroke. 5.4, the TCAD results also indicate an increase in the SET pulse width when scaling from 130 nm to 90 nm.

TCAD simulations were also performed to identify the effect of contact width, device reset W/L, and power supply voltage on the SET pulse width in the 90 nm process. Finally and most interesting is the effect of load inverter scale size on SET pulse width. The size of the loading gate was found to have only a small effect on the SET pulse width.

The reduction in drive currents and contact sizes can tend to increase the SET pulse width with scaling. Based on the dependence of the TCAD simulated SET pulse width in the 90 nm process of LET, recovering the driving current, supply voltage and contact width, a mathematical model for the SET pulse width is developed. Two SET pulse characterization test structures are designed on the same IC in the IBM 130 nm process.

5.9 (a) is a graph of the maximum SET pulse width for the conventional layout circuit and for the guardband circuit. However, both the TCAD results and the experimental results show that the drive power reset can significantly affect the SET pulse width. Possible reasons for the similarity in SET pulse width distributions in the 90 nm process at different LETs.

There was only a small increase in mean and maximum SET pulse width at higher LETs compared to lower LETs. The simulation results suggest about 50%. increase in the SET pulse width due to lowering the drive current by about a factor of two. Thus, the lower drive current may have a role in the experimentally observed SET pulse width distribution.

These results suggest that the ion track diameter can affect the SET pulse width at lower LETs. Furthermore, the increase in the SET pulse width will vary from approx. 0 ps (for strokes in the target inverter chain close to the measurement circuit) to 350 ps (for strokes at the beginning of the target inverter chain).

Fig. 4.10 Variation in the SET width relative to strike location from well contact.

DUT boards

The neutron beam penetrates the printed circuit boards with minimal flux loss, making it possible to test multiple chips simultaneously. A total of 20 SET events were measured during this test time, ranging from approximately 300 ps to approximately 1.4 ns. Based on the layout, the sensitive area of an inverter used in this design is approximately 0.75 µm2.

The low number of events is attributed to the small surface area of the target circuits and to the fact that neutrons ionize indirectly via secondary reaction products.

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