EAST WEST INSTITUTE OF TECHNOLOGY
DEPARTMENT OF INFORMATION SCIENCE & ENGG.
COURSE FILE
2022-23 Semester – V
Department of Information Science
& Engineering
Name : Ashwini R
Designation : Assistant Professor
VISION
To be an Institute of Academic Excellence in Technical and Management Education on par with global standards to meet changing needs of the Society.
MISSION
To impart quality technical education that nurtures the young minds by providing the best of teaching learning process and state of the art infrastructure.
To foster technological advancement through research.
To inculcate holistic personality development through best practices.
To implant ethical and social commitment that grooms the students to become responsible citizens.
OBJECTIVES
To enhance capacity development in the institution
Attaining excellence in teaching – faculties and methodologies
Improving competency of staff and student
Enhancing institution industry collaboration
Strengthening academic reforms in the institution
To nurture the holistic development of students community
To impart quality oriented teaching pedagogies in enriching young minds.
Program Outcomes:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and engg. specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, research literature, and analyze engineering problems to arrive at substantiated conclusions using first principles of mathematics, natural, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design system components, processes to meet the specifications with consideration for the public health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modeling to complex engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal, and cultural issues and the consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in teams, and in multidisciplinary settings.
10. Communication: Communicate effectively with the engineering community and with society at large. Be able to comprehend and write effective reports documentation. Make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of engineering and management principles and apply these to one’s own work, as a member and leader in a team. Manage projects in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and lifelong learning in the broadest context of technological
change.
Program Specific Outcomes (PSOs)
PSO1: Graduates will be able to understand and apply technical knowledge and skills to solve real time problems in the field of information science and engineering.
PSO2: Graduates can analyze, design and implement the innovative ideas to model real world’s problems using programming and algorithms to provide solutions with Ethical and management principles
INDEX
SL.NO CONTENTS
1 Students List
2 Calendar of Events
3 Course Plan
4 IA paper and Schema
ANALOG AND DIGITAL ELECTRONICS
Course Code 21CS33 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40 T + 20 P Total Marks 100
Credits 04 Exam Hours 03
Course Learning Objectives:
CLO 1. Explain the use of photo electronics devices, 555 timer IC, Regulator ICs and uA741 CLO 2. Make use of simplifying techniques in the design of combinational circuits.
CLO 3. Illustrate combinational and sequential digital circuits CLO 4. Demonstrate the use of flipflops and apply for registers
CLO 5. Design and test counters, Analog-to-Digital and Digital-to-Analog conversion techniques.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teachers can use to accelerate the attainment of the various course outcomes.
1. Lecturer method (L) does not mean only traditional lecture method, but different type of teaching methods may be adopted to develop the outcomes.
2. Show Video/animation films to explain functioning of various concepts.
3. Encourage collaborative (Group Learning) Learning in the class.
4. Ask at least three HOT (Higher order Thinking) questions in the class, which promotes critical thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills such as the ability to evaluate, generalize, and analyze information rather than simply recall it.
6. Topics will be introduced in a multiple representation.
7. Show the different ways to solve the same problem and encourage the students to come up with their own creative ways to solve them.
8. Discuss how every concept can be applied to the real world - and when that's possible, it helps improve the students' understanding.
Module-1
BJT Biasing: Fixed bias, Collector to base Bias, voltage divider bias Operational Amplifier Application Circuits: Peak Detector, Schmitt trigger, Active Filters, Non-Linear Amplifier, Relaxation Oscillator, Current-to-Voltage and Voltage-to-Current Converter, Regulated Power Supply Parameters, adjustable voltage regulator, D to A and A to D converter.
Textbook 1: Part A: Chapter 4 (Sections 4.2, 4.3, 4.4), Chapter 7 (Sections 7.4, 7.6 to 7.11), Chapter 8 (Sections 8.1 and 8.5), Chapter 9.
Laboratory Component:
1. Simulate BJT CE voltage divider biased voltage amplifier using any suitable circuit simulator.
2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle
3. Design an astable multivibrator circuit for three cases of duty cycle (50%, <50% and >50%) using NE 555 timer IC.
4. Using ua 741 opamap, design a window comparator for any given UTP and LTP.
Teaching-Learning Process 1. Demonstration of circuits using simulation.
2. Project work: Design a integrated power supply and function generator operating at audio frequency. Sine, square and triangular functions are to be generated.
3. Chalk and Board for numerical Module-2
Karnaugh maps: minimum forms of switching functions, two and three variable Karnaugh maps, four variable Karnaugh maps, determination of minimum expressions using essential prime implicants, Quine- McClusky Method: determination of prime implicants, the prime implicant chart, Petricks method, simplification of incompletely specified functions, simplification using map-entered variables Textbook 1: Part B: Chapter 5 (Sections 5.1 to 5.4) Chapter 6 (Sections 6.1 to 6.5) Laboratory Component:
1. Given a 4-variable logic expression, simplify it using appropriate technique and inplement the same using basic gates.
Teaching-Learning Process 1. Chalk and Board for numerical 2. Laboratory Demonstration
Module-3
Combinational circuit design and simulation using gates: Review of Combinational circuit design, design of circuits with limited Gate Fan-in, Gate delays and Timing diagrams, Hazards in combinational Logic, simulation and testing of logic circuits
Multiplexers, Decoders and Programmable Logic Devices: Multiplexers, three state buffers, decoders and encoders, Programmable Logic devices.
Textbook 1: Part B: Chapter 8, Chapter 9 (Sections 9.1 to 9.6) Laboratory Component:
1. Given a 4-variable logic expression, simplify it using appropriate technique and realize the simplified logic expression using 8:1 multiplexer IC.
2. Design and implement code converter I) Binary to Gray (II) Gray to Binary Code Teaching-Learning Process 1. Demonstration using simulator
2. Case study: Applications of Programmable Logic device 3. Chalk and Board for numerical
Module-4
Introduction to VHDL: VHDL description of combinational circuits, VHDL Models for multiplexers, VHDL Modules.
Latches and Flip-Flops: Set Reset Latch, Gated Latches, Edge-Triggered D Flip Flop 3,SR Flip Flop, J K Flip Flop, T Flip Flop.
Textbook 1: Part B: Chapter 10(Sections 10.1 to 10.3), Chapter 11 (Sections 11.1 to 11.7) Laboratory Component:
1. Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same in HDL simulator
2. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And implement the same in HDL.
Teaching-Learning Process 1. Demonstration using simulator
2. Case study: Arithmetic and Logic unit in VHDL 3. Chalk and Board for numerical
Module-5
Registers and Counters: Registers and Register Transfers, Parallel Adder with accumulator, shift registers, design of Binary counters, counters for other sequences, counter design using SR and J K Flip Flops.
Textbook 1: Part B: Chapter 12 (Sections 12.1 to 12.5)
Laboratory Component:
1. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and demonstrate its working.
2. Design and implement an asynchronous counter using decade counter IC to count up from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447)
Teaching-Learning Process 1. Demonstration using simulator
2. Project Work: Designing any counter, use LED / Seven- segment display to display the output
3. Chalk and Board for numerical Course outcome (Course Skill Set)
At the end of the course the student will be able to:
CO 1. Design and analyze application of analog circuits using photo devices, timer IC, power supply and regulator IC and op-amp.
CO 2. Explain the basic principles of A/D and D/A conversion circuits and develop the same.
CO 3. Simplify digital circuits using Karnaugh Map, and Quine-McClusky Methods
CO 4. Explain Gates and flip flops and make us in designing different data processing circuits, registers and counters and compare the types.
CO 5. Develop simple HDL programs
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be deemed to have satisfied the academic requirements and earned the credits allotted to each subject/ course if the student secures not less than 35% (18 Marks out of 50) in the semester-end examination (SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together
Continuous Internal Evaluation:
Three Unit Tests each of 20 Marks (duration 01 hour) 1. First test at the end of 5th week of the semester 2. Second test at the end of the 10th week of the semester 3. Third test at the end of the 15th week of the semester Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester 5. Second assignment at the end of 9th week of the semester
Practical Sessions need to be assessed by appropriate rubrics and viva-voce method. This will contribute to 20 marks.
Rubrics for each Experiment taken average for all Lab components – 15 Marks.
Viva-Voce– 5 Marks (more emphasized on demonstration topics)
The sum of three tests, two assignments, and practical sessions will be out of 100 marks and will be scaled down to 50 marks
(to have a less stressed CIE, the portion of the syllabus should not be common /repeated for any of the methods of the CIE. Each method of CIE should have a different syllabus portion of the course).
CIE methods /question paper has to be designed to attain the different levels of Bloom’s taxonomy as per the outcome defined for the course.
Semester End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks. Marks scored shall be proportionally reduced to 50 marks
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum of 3 sub-questions), should have a mix of topics under that module.
The students have to answer 5 full questions, selecting one full question from each module Suggested Learning Resources:
Textbooks
1. Charles H Roth and Larry L Kinney, Raghunandan G H Analog and Digital Electronics, Cengage Learning,2019
Reference Books
1. Anil K Maini, Varsha Agarwal, Electronic Devices and Circuits, Wiley, 2012.
2. Donald P Leach, Albert Paul Malvino & Goutam Saha, Digital Principles and Applications, 8th Edition, Tata McGraw Hill, 2015.
3. M. Morris Mani, Digital Design, 4th Edition, Pearson Prentice Hall, 2008.
4. David A. Bell, Electronic Devices and Circuits, 5th Edition, Oxford University Press, 2008 Weblinks and Video Lectures (e-Resources):
1. Analog Electronic Circuits: https://nptel.ac.in/courses/108/102/108102112/
2. Digital Electronic Circuits: https://nptel.ac.in/courses/108/105/108105132/
3. Analog Electronics Lab: http://vlabs.iitkgp.ac.in/be/
4. Digital Electronics Lab: http://vlabs.iitkgp.ac.in/dec
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
1. Real world problem solving - applying the design concepts of oscillator, amplifier, switch, Digital circuits using Opamps, 555 timer, transistor, Digital ICs and design a application like tone generator, temperature sensor, digital clock, dancing lights etc.
Course Prerequisites:
Basic knowledge of the Analog and digital Electronics which includes Semiconductor devices, number system and basic gates.
Course Overview and its relevance to program:
Analog and Digital Electronic Circuits is one of the important subject in a course in Computer Science and Engineering discipline. An electronic circuit is composed of individual electronic components ( resistors, transistors, capacitors, inductors and diodes, connected by conductive wires or traces through which electrical current can flow. The combination of components and wires allows various simple and complex operations to be performed: signals can be amplified, computations can be performed, and data can be moved from one place to another.
Hence, the knowledge of Analog electronic to study the behavior of electronic components and Digital electronics to design complex logics is necessary.
This course covers wide range of topics related to analog electronics, which includes
the study of transistors, BJT biasing. The course also covers the applications of OP-Amps and
IC-Timers. In digital electronics, the course covers wide range of digital devices and designing
of digital circuits. It deals with basics of digital logic and logic gates as building blocks of
digital design. It enables students to design complex circuits using logic gates, simplifying
circuits using Boolean Algebra, K-maps and Quine-McCluskey methods. The course also
discusses the design and applications of higher level digital circuits- Multiplexers, decoders,
comparators, ALU, Flip flops, Shift registers etc. The students will be able to design different
counters using different flip flops. It deals with the study of different techniques related to
Analog to Digital conversion (ADC) and Digital to Analog Conversions (DAC). The course
also enables students to understand and use one high-level hardware description languages
(VHDL or Verilog) to design combinational or sequential circuits. The design process for
today's billion-transistor digital systems becomes a more programming-based process than
before and hence programming skills are important.
MODULE-1 MODULE WISE PLAN
Module Numbers: 1 No. of Hours: 10
Learning Objectives: At the end of this module students will be able to:
1.
Understand Transistor and various BJT biasing2.
Multivibrator circuits configuration around digital integrated circuits, Multivibrator circuits configured around timer IC 5553.
Difference between an ideal and practical opamp Peak Detector Circuit, Absolute Value Circuit Comparator, Active Filters, Phase Shifters Non-Linear Amplifier, Relaxation Oscillator Current-To-Voltage Converter, Voltage-To-Current Converter, Sine Wave OscillatorsLesson Plan:
Lecture
No. Topics Covered Teaching Method
POs Attained
PSOs Attained
COs Attained
Text or Reference Book/Chapter
No.
BJT Biasing: Fixed bias, Collector to base Bias
Chalk &
L 21 Board, 1, 2 T1/5
PPT
1,2,3,4,5,11 1,2,3
L 22
Collector to base Bias, voltage divider bias
Chalk &
Board, PPT
1 T1/5
L 23
Operational Amplifier Application Circuits: Peak Detector
Chalk &
Board,
PPT 2, 3 T1/5
L 24
Wave-Shaping Circuits:
Integrated Circuit (IC)
Multivibrators.
Chalk &
Board, PPT
2, 3 T1/13
L 25
Introduction to Operational Amplifier: Ideal v/s practical Opamp, Performance Parameters,
Chalk &
Board, PPT
1,2 T1/16
L 26
Operational Amplifier Application Circuits: Peak Detector Circuit,
Chalk &
Board, PPT
3 T1/16
L 27 Comparator
Chalk &
Board, PPT
2,3 T1/16
L 28 Active Filters
Chalk &
Board, TPS
2,3 T1/16
L 29
Non-Linear Amplifier, Relaxation Oscillator
Chalk &
Board, PPT
2, 3 T1/16
L 30
Current-To- Voltage Converter, Voltage-To- Current Converter
Chalk &
Board, PPT
2,3 T1/16
Questions for practice:
1. Explain various BJT biasing 2.
2 An experimental setup using a BJT gave the following readings:
a. With VGS=0V and VDS=15V, ID=15mA b. With VGS=0V and VDS=10V, ID=14mA
c. With VGS=-1V and VDS=15V, ID=13mA Determine the values of
a.
Drain resistanceb.
Transconductancec.
Amplification factor2,3
3. With the help of circuit diagram briefly describe the operation of timer IC based astable multivibrator in which output HIGH and LOW state time periods can be set independently.
2 4. How would you characterize an ideal opamp? How does a practical opamp
differ from an ideal opamp? Use Thevinin’s equivalent circuit model to comparator an ideal opamp with a practical opamp.
1 5. What is primarily responsible for given an opamp the following characteristic?
a. High input impedance b. Low output impedance c. High open loop gain
d. High common mode rejection ratio e. Frequency response down to DC f. CMRR
1
6. Briefly describe the following types of opamp with reference to major performance parameters.
a. Slew rate b. Open loop gain c. Setting time
1
7. What is the main advantage of using a comparator with hysteresis over a conventional comparator? Explain with the help of relevant transfer characteristics.
1,2 8. With the help of relevant circuit schematic of a non-inverting comparator with
hysteresis, briefly describe its operation and draw its transfer characteristics 1,2 9. Design an opamp based current to voltage converter having a Tranresistance
gain of 100,000. 3
10. Design a non inverting aero crossing detector with a hysteresis of 100mV. If the opamp had output saturation voltage of ±10V, determine the highest input frequency that would yield output waveform transition time of not more than
10% of half of the time period of input signal. Chosen opamp has slew rate of 10V/µs.
3
MODULE-2 MODULE WISE PLAN
Module Numbers: 2 No. of Hours: 10
Learning Objectives: At the end of this module students will be able to:
1.
Write the truth tables and draw the symbols for OR, AND, NOT, NOR, and NAND gates.2.
Demonstrate the ability to use basic Boolean laws.3.
Use the sum-of-products method to design a logic circuit based on a design truth table.4.
Be able to make Karnaugh maps and Entered variable maps and use them to simplify Boolean expressions.5.
Use the product-of-sums method to design a logic circuit based on a design truth table.6.
Use Quine-McClusky tabular method for logic simplification.7.
Analyze hazards in logic circuit and provide solution for them.8.
HDL Implementation Models Lesson Plan:Lecture No.
Topics Covered
Teaching Method
POs Attained
PSOs Attained
Cos Attained
Text or Reference Book/Chapter
No.
L 01.
Basic gates NOT, OR,
Chalk &
Board, 1 T2/2
AND PPT
Universal Logic Chalk &
L 02
Gates NOR, Board, 1 T2/2AND PPT
L 03
Positive and Negative LogicChalk &
Board, PPT
1 T2/2
L 04
Introduction to HDLChalk &
Board, PPT
1 T2/2
L 05
Sum of- products
Chalk &
Board,
1,2,3,4,5,11 1,2,3
1 T2/3
Method PPT
L 06
Truth Table to Karnaugh Map, Pairs, Quads and Octets
Chalk &
Board, PPT
2,3 T2/3
Karnaugh
L 07
Simplifications Don’t Care Conditions, Product-of-
Chalk &
Board, PPT
2,3 T2/3
sums Method
L 08
Product-of- Chalk &2,3 T2/3
sums Board,
Simplification PPT
L 09
Simplification by Quine- McClusky Method
Chalk &
Board, PPT
2,3 T2/3
L 10
Hazards and Hazard Covers, HDL
Implementation Models
Chalk &
Board, PPT
2,3 T2/3
Questions for Practice:
Questions COs attained
1.
Construct 3-I/O AND gate and 3 – I/O OR gate 1,22.
What are universal gates? Realize basic gates using only NAND gates. 1,33.
What is the purpose of using an expander with an AND-OR-INVERT gate?Write a logic circuit of an expander driving expandable AND-OR-INVERT gate.
1,3
4.
Implement the following function using universal gates only((A+B)C)D 3
5.
Write the truth table of the logic circuits having 3 inputs A,B,C and the output expressed asY= A B C + A B C + A B C + A B C
Also simplify the expression using Boolean algebra and implement the logic circuit
3
6.
Simplify the following logic equation using Karnaugh map and give theimplementation of the simplified expression
F(A,B,C,D)=∑m(7) + d(10,11,12,13,14,15)
3
7.
What are the drawbacks of K-map? Simplify the following Quine-McClusky method F(A,B,C,D)=∑ (0,1,2,3,10,11,12,13,14,15) 2,3
8.
Find Product Of SumY= A B + A C + A D 3
9.
Suppose a 4 input combinational logic circuit has high output for an input of 0000, low output, for 0001 to 1001 and don’t care s for 1010 to 1111 what is the simplest logic circuit draw the truth table.3
MODULE-3 MODULE WISE PLAN
MODULE Numbers: 3 No. of Hours: 10
Learning Objectives: The main objectives of this module are to:
1.
Determine the output of a multiplexer or demultiplexer based on input condition2.
Find, based on input conditions, the output of an encoder or decoder3.
Draw the symbol and write the truth table for an exclusive-OR gate4.
Explain the purpose of parity checking5.
Show how a magnitude comparator works6.
Describe a ROM, PROM, EPROM, PAL and PLA7.
Describe characteristic equations of Flip-Flops and analysis techniques of sequential circuits8.
Describe excitation table of Flip-Flops and explain Conversion of Flip-Flops as synthesis example9.
Describe operation of basic RS flip-flop and explain the purpose of the additional input on the gated RS flip-flop10.
Show the truth table for the edge-triggered. RS flip-flop, edge-triggered D flip-flop, and edge-triggered JK flip-flop and describe its operation.Lesson Plan:
Lecture
No. Topics Covered Teaching Method
POs attained
PSOs Attained
COs attained
Reference Book/
Unit No.
L11.
Multiplexers, DemultiplexersChalk &
Board, PPT
1,2 T2/4
L12.
1-of-16 Decoder , BCD- to-Decimal DecodersChalk &
Board, PPT
1,2 T2/4
L13.
Seven-segment Decoders, EncodersChalk &
Board, PPT
1,2 T2/4
L14.
EX -OR gates, Parity Generators and
Chalk &
Board, 1,2 T2/4
Checkers PPT
L15.
Magnitude Comparator, Programmable Array
Chalk &
Board, 2,3 T2/4
Logic PPT
L16.
Programmable Logic Array, HDL
Implementation of Data Processing Circuits
Chalk &
Board, PPT
1,2,3,4,5,11 1,2,3
2, 3 T2/4
L17.
Arithmetic Building Blocks, Arithmetic
Chalk &
Board, 2 T2/6
Logic Unit PPT,
L18.
Flip- Flops: RS Flip- Flops Gated Flip-Flops, Edge-triggered RS FLIP- FLOP
Chalk &
Board, PPT
1,2 T2/8
L19.
Edge triggered D FLIP-FLOPsChalk &
Board, PPT
1,2 T2/8
L20.
Edge-triggered JK FLIP- FLOPs.Chalk &
Board, PPT
1,2 T2/8
Questions for practice:
Questions COs attained
1.
Design a 32 to 1 multiplexer using two 16 to 1 multiplexer and one 2 to 1 3multiplexer
2.
Show that using a 3 to 8 decoder and multi-input OR gate. The following Boolean expressions can be realizedF1(A,B,C) = ∑m(0,4,6) F2(A,B,C) = ∑m(0,54,6) F3(A,B,C) = ∑m(1,2,3,7)
3
3.
Show how two 1 to 16 demultiplexer can be connected to get a 1 to 32demultiplexers. 3
4.
Design Decimal to BCD encoder 35.
What are different types of PLD’s and implement the 7-segment decoderusing PLA? 2,3
6.
What is a magnitude comparator? Write the truth table and circuit diagramof 1 bit comparator 1,2
7.
Give verilog HDL code for 4-to-1 multiplexer using conditional assign andcase statements 3
8.
Write verilog code for a combinational logic circuit that compares two 4-bit output numbers A and B generates a 3-bit output Y. The 3-bits of Y represent A=B, A>B & A<B3
9.
Explain the different types of flip flops along with their truth table. Alsoexplain the race around condition in flip flop 1,2
MODULE-4 MODULE WISE PLAN
Module Numbers: 4 No. of Hours: 07
Learning Objectives: The main objectives of this module are to:
1. Show the truth table for the edge-triggered. RS flip-flop, edge-triggered D flip-flop, and edge-triggered JK flip-flop and describe its operation.
2. State the cause of contact bounce and describe a solution for this problem.
3.
Understand serial in-serial out, serial in-parallel out, parallel in- parallel out, parallel in- serial out shift registers and be familiar with the basic features of the 74LS91, 74166, 74LS91, 74174 and 7495A register.
4.
State various uses of shift register5.
Implementation in HDLLesson Plan:
Lecture
No. Topics Covered Teaching Method
POs attained
PSOs attained
COs attained
Reference Book/
Unit No.
L 31
FLIP-FLOP Timing, JK Master-slave FLIP- FLOP, Switch Contact, Bounce Circuits
Chalk &
Board, PPT
1,2,3,4,5,11 1,2,3
1,2 T2/8
L 32
Various Representation of FLIP-FLOPs,
HDL Implementation of FLIP-FLOP.
Chalk &
Board, PPT 1,2 T2/8
L 33
Types of Registers Chalk &Board, PPT 1 T1/9
L 34
Serial In-Serial Out, Serial In-Parallel OutChalk &
Board, PPT 1 T1/9
L 35
Parallel In-Serial Out, Parallel In-Parallel Out,Chalk &
Board, PPT 1 T1/9
L 36
Universal Shift Register Chalk &Board, PPT 1 T1/9
L 37
Applications of Shift RegistersChalk &
Board, PPT 2,3 T1/9
L 38
Register Implementation in HDL, Asynchronous Counters
Chalk &
Board, PPT 2 T1/9,10
L 39
Decoding Gates, Synchronous CountersChalk &
Board, PPT 2,3 T1/10
L 40
Changing the Counter Modulus.Chalk &
Board, PPT 2,3 T1/10
Questions for practice:
Questions COs attained
1.
Explain a 4 bit serial input shift register in details and give its timingdiagram 1,2
2.
Design a mod-5 synchronous up counter using JK Flip-flop 33.
Write Verilog code for switched-tail counter using ‘assign’ and ‘always’statements 2,3
4.
Explain ant two types of shift register with waveforms. How Johnsoncounter is obtained from shift register? 1,2
5.
Mention the differences between ripple and synchronous counters. 16. Realize the sequential circuit for the state diagram shown below in
3
7. Show how to convert d flip flop to JK flip-flop
1,2 MODULE-5MODULE WISE PLAN
MODULE Numbers: 5 No. of Hours: 10
Learning Objectives: The main objectives of this module are to:
1. Design and implement Decade Counters, Pre settable Counters 2. Understand Counter Design as a Synthesis problem
3. Be able to do calculations related to variable resistor and binary ladder networks.
4. Recall some of the sections of a typical D/A resolution.
5. Understand A/D conversion using the simultaneous, counter, continuous and dual 6. Discuss the accuracy and resolution of A/D converters
Lesson Plan:
Lecture
No. Topics Covered Teaching Method
POs attained
PSOs attained
COs attained
Reference Book/
Unit No.
L 41 Decade Counters
Chalk &
Board, PPT
1,2,3,4,5,11 1,2,3
2,3 T1/10
L 42
Pre settable Counters, Counter Design as a Synthesis Problem
Chalk &
Board, PPT
2,3 T1/10
L 43 A Digital Clock
Chalk &
Board, PPT
2 T1/10
L 44 Counter Design using HDL
Chalk &
Board, PPT
2,3 T1/10
L 45
Variable, Resistor Networks, Binary Ladders
Chalk &
Board, PPT
2,3 T1/12
L 46
D/A Converters, D/A Accuracy and
Resolution A/D Converter- Simultaneous Conversion
Chalk &
Board, PPT
1,2 T1/12
L 47 A/D Converter- Counter Method
Chalk &
Board, PPT
1,2 T1/12
L 48
Continuos A/D Conversion, A/D Techniques,
Chalk &
Board, PPT
1,2 T1/12
L 49 Dual-Slope A/D Conversion
Chalk &
Board, PPT
1,2 T1/12
L 50 A/D Accuracy and Resolution
Chalk &
Board, PPT
1,2 T1/12
Questions for practice:
Questions COs attained 1. Draw the gates necessary to decode the 16 states of mod-16 counter
7493. What are decoding glitches? How to eliminate them? 3 2. What are pre-settable counters? What is lock out of a counter? Show
how to construct mod-13 counter ring using 74163 synchronous binary counter IC
2,3 3. Explain ripple counter(Asynchronous counter) with truth table and
wave form 2
4. Design a self-correcting mod-6 counter as described in the state sequence of figure given below in which all the unused states leads to state CBA=000
2,3
5. With the help of a suitable example, explain the following operations in a shift register.
i)
SISO ii) PISO iii)Twisted ring counter
2 6. Name and explain the four basic types of shift registers and draw a
block diagram for each. 1
7. What is a binary ladder? Explain the binary ladder with a digital input
of 1000 1,2
8. Explain a 2- bit simultaneous A/D converter 1,2
9. What is accuracy and resolution of D/A converter? What the
resolution of a 12 bit D/A converter which uses a binary ladder? If the full-scale output is +10v, what is the resolution in volts?
1,3
10. Explain successive approximation A/D converter 1
11. Find the following for a 12-bit counter-type A/D converter using a 1- MHz clock
i) Maximum conversion time ii) Average conversion time iii) Maximum conversion rate
1,3
ASSIGNMENT QUESTIONS
ASSIGNMENT - I COs attained
Q.1. Simplify using K-maps F(a,b,c,d)= Min(7) +d(10,11,12,13,14,15) to
Min. SoP and PoS forms. 3
Q.2. Write HDL codes using –Structural Model, Dataflow Model and
Behavioural Model for Y = ~A+B.~C 2,3
Dept of ISE, EWIT, Bangalore.
Q.3. Simplify using Quine-Mc Clusky Method:
F(w,x,y,z) = Min( 1,2,3,4, 7,8,9,10, 15) 3
Q.4. Design the HDL implementation of JK-Flipflop 3
Q.5. Design a Mod 9 ripple up counter. 2,3,4,6
Q.6. Write – Characteristics Table, Transition Table, Characteristic
equation and State Diagram for RS, JK, D and T- flip flops. 1,2
ASSIGNMENT - II COs attained
Q.1. Design F(w,x,y,z) = Min( 1,2,3,4, 7,8,9,10, 15) using 16x1 MUX and
8x1 MUX 3
Q.2. Design F(a,b,c) = Min(2,5,6) using 3 to 8 Decoder. 3 Q.3. Design the PLA implementation of F(a,b,c) = Min(2,3,5,6,7) 3 Q.4. Differentiate between BJT and FET, JFET and MOSFET. Explain
CMOS inverters. 1
Q.5. Explain Monostable multivibrator using 555 Timer. 1 Q.6. Design a second order LP filter – with Cutoff frequency 15 KHz, and
Gain 20dB. Draw the frequency response plots. 3
ASSIGNMENT - III COs attained
Q.1. Design 4-bit PISO Shift reister. If clock is 10MHz, find the time
require to input 4-bit data and read 4-bit data from SR. 3
Q.2. Design Mod 10 Synchronous UP Counter 3
Q.3. Design Mod 6 Synchronous Down counter 3
Q.4. Explain the design of Digital clock 2,3
Q.5. Discuss the HDL implementations of MOD 5 up counter using JK
flipflop. 3
Q.6. Design a 4-bit R-2R ladder DAC. Assume Vref=10V. 3
PORTION FOR THE I.A. TESTTest Modules
IA Test –I Module-1, Module-2
IA Test –II Module-3, Module-4
IA Test –III Module-5