effects of total-ionizing dose on carbon nanotube

Last but not least, I would like to thank my wife Jenna for all her support and assistance during my transition from the military to the life of a graduate student. The vacuum baking caused no noticeable change in the IV curves of the Lot 1 transistors. All this is possible thanks to the doubling of the number of transistors that fit on an integrated circuit every year or two, as observed by Gordon Moore [1].

Additionally, low-frequency noise (LFN) testing both before and after TID irradiation can provide insight into the nature and density of defects in the oxides used in the transistors and can inform the mechanisms of the TID response. The goal of the research described in this thesis was to perform a TID test campaign on the CNTFETs developed for the 3DSOC program. Imperfections in the oxide can cause some of the mobile holes to be trapped in the oxide in what are called oxide traps [17], Fig. 2.1 (3).

The positive charge of trapped holes in the oxide degrades the performance of the semiconductor device.

Low-Frequency Noise

Initial studies on high-k dielectrics have shown high defect density relative to SiO2 and increased sensitivity to the effects of TID [23]. The electrons are quickly swept away, leaving behind holes that move relatively slowly toward the oxide/semiconductor interface. As the holes move, some hydrogen ions are released that travel to the interface, where they interact with dangling Si bonds [14].

Low frequency noise testing on CNTFETs therefore has the potential to provide first order estimates of defect densities in the oxides and combined with further theory calculations can facilitate the identification of the defect microstructures.

Carbon Nanotube Field Effect Transistor Construction and History

DREAM works during logic synthesis to create logic functionality by avoiding the combinations most susceptible to metallic CNTs [27]. Transistors consist of a bottom metal gate with CNTs in the channel above connecting the metal source and drain. Note the differences between PMOS and NMOS with different drain/source metals and surrounding oxides [27].

MIT CNTFETS

The original CNTFETs used a non-standard metal evaporation and lift-off to remove the CNTs outside the channel and create the metal source/drain contacts. In the lift-off free process, an Al2O3 mask covers and protects the CNTs in the channels during plasma etching. Another difference in the new process is the source and drain metals - Ti/TiW and W for NMOS and PMOS respectively.

In Lot 3, the NFETs and PFETs are created entirely by the work function engineering in the contact between the SWCNTs and the metal drain/source, rather than by electrostatic tuning using surrounding oxides. The Al2O3 is deposited by atomic layer deposition and is a hard mask used to protect the CNTs during dry etching of the contact holes.

Figure 2.3 – Illustration depicting the fabrication flow constructing Lot 1 and Lot 2 CNTFETs [27]

CNTFET Response to TID

The bottom gate is made of tungsten and the gate dielectric is a mixture of hafnium oxide and aluminum oxide.

Electrical Characterization Testing Setup

A series of electrical characterization tests were performed to separate the curve differences between the IDS-VGS transistors caused by TID or operational/test stress. The probe pads are the large square surfaces arranged in rows and columns on the die. After receiving the CNTFETs, IDS-VGS data were acquired to establish a preliminary baseline.

Before any testing took place, the transistors were baked in an attempt to anneal any contamination that may have accumulated from storage in air and humidity during transport to Vanderbilt. A new procedure was used for Lot 2 and Lot 3: these lots were baked in nitrogen at 300 degrees Celsius for five minutes to anneal out any moisture. The transistor IDS-VGS curves before and after baking were compared, and the results are shown in section 3.2.

The next test requires the transistors to be biased for the same time that the transistors will be biased during radiation in either a simulated ON state or a negative gate bias state. These times correspond to the amount of time the device would be biased for the six TID levels used in the radiation test. Additionally, multiple IDS-VGS sweeps were performed in rapid-sequence devices to determine time-induced stress under bias from stress induced by I-V sweeps.

The multiple sweep tests served to determine whether the control stress was caused by the time under bias or the stress of the seven I-V sweeps. A hysteresis test was performed, where the IDS-VGS was swung from a negative gate voltage to a positive gate voltage, and then from a positive gate voltage to a negative gate voltage. Hysteresis is a known effect in CNTFETs and this test quantified the amount in the transistors used in this research.

Figure 3.1 – Image of Lot 2 die surface. Each column contained different types of test devices

Sweeps

The transistor was swept ten times in the negative to positive VG direction and ten times in the positive to negative VG direction.

Hysteresis

Lot 1
Lot 2

3.8, the newer transistors exhibited approximately 0.5 V less hysteresis shift than the earlier series of transistors. All control and TID tests for Lot 3 transistors will show curves taken with VG from negative to positive. 3.9 showed that the CNTFETs were affected by being in the ON state during a TID test.

A voltage shift to the positive indicates electrons trapped in intermediate traps [51] or in oxide traps formed from oxygen vacancies in the dielectric [54]. Electrons are trapped by hot carrier injection, where electrons accelerated in the channel gain enough energy to be injected into the gate dielectric [51]. This test shows a positive bias voltage shift in the ON state for a total of 33 minutes.

This positive IDS-VGS shift is caused by the positive voltage on the gate leading to electron trapping in the gate dielectric [54], similar to the Lot 1 results. The negative voltage on the gate caused the I-V curves to shift to the left, caused by holes trapped in the oxide [55]. The Lot 3 control test shows no noticeable curve shifts compared to the first two lots.

All of the electrical characterization tests combined to show how these transistors were affected by normal operation and test voltage. In addition, the results of the control stress test and the hysteresis test indicate a large number of defects in the oxides that can trap charge. This suggests that these CNTFETs will be susceptible to the effects of TID-induced charge trapping.

Figure 3.7 – Lot 2 transistors exhibiting hysteresis. Note the 0.5 V difference between a negative to positive sweep and a positive to negative sweep

Total-Ionizing-Dose Experiment Setup

CNTFET Response to TID

Lot 1 Results
Lot 2 Results
Lot 3 Results
Summary of TID Results

Lot 2 CNTFETS also show significant negative threshold voltage shifts with dose, shown in Fig. The three lots also showed similar increases in current at 0 V VG, as shown in Figure 4.10. The Lot 1 and Lot 3 transistors had a current increase of approximately 1 order of magnitude, and the Lot 2 CNTFETs had a current increase of three orders of magnitude.

Previous research suggests that the source of hysteresis in CNTFETs is defects in the oxides [45][66]. Although the channel material used in a CNTFET is CMOS-proportional, the CNTFET device still has a gate dielectric and oxides surrounding the entire transistor, and the TID response depends on the oxides used in the devices. The structure of the CNTFETs in this research is similar to a fully depleted silicon-on-insulator (FDSOI) MOS transistor.

The channel is lightly doped silicon, which is analogous to the undoped carbon nanotube semiconductors in the CNTFET channel. The drain, source, and channel sit on top of a buried oxide (BOX), which is structurally similar to a CNTFET layout. FDSOI devices have shown increased sensitivity to TID effects due to charge trapping in the BOX [62].

This charge results in a threshold voltage shift, in contrast to modern FinFETs where the primary effect of TID is to increase the leakage current [64]. This is similar to the CNTFET results, which show a large shift in VTH with dose, indicating that the oxide above the CNTs traps charge. The image shows a lightly doped p-channel between the source and the drain and on top of the buried oxide (BOX).

More charge trapping defects are also depicted in the larger BOX than in the gate oxide [62]. The larger VTH shift in CNTFETs compared to FDSOIs is due to the increased number of defects in the oxides surrounding the transistors.

Figure 4.7 – TID results for Lot 3 CNTFETs with the gate biased in an OFF-bias condition

Low-Frequency Noise Experiment Setup

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