Relative location of the three operating areas of a power MOSFET in sufficiently high LET. Figure 5b is a cross-section through the XZ plane of a diode, and Figure 5c is a top view of the MOSFET under the metallization. 11a at peaks and valleys along the X-axis, as well as a sweep of the diode along the Z-axis.
14b shows TCAD simulations of collected charge in a diode for a constant amount of deposited charge, but varying location and bias. 14c shows TCAD simulations of collected charge in a MOSFET and diode for a constant amount of deposited charge and constant location, but varying bias. Second peaks of collected charge as a function of the drain bias under the bias voltage.
A distribution of charge collection values was collected for each bias and ion species, and the points shown are the higher of the two most frequently collected charge bins in each distribution.
Experimental Techniques Available
Heavy Ion, Proton, and Neutron Testing
When testing, SEGR can be distinguished from SEB by monitoring the drain and gate currents, as shown in Fig. In an SEGR, the damage to the gate results in a permanent current increase through the gate, whereas an SEB may result in a capacitive spike in gate current but no sustained effect. In both cases, the destructive nature is due to allowing for a sustained negative drain current large enough to cause harmful power loss.
Experimental drain and gate currents for single-event gate rupture and single-event burnout, respectively, as observed and processed by Akturk et al.
TCAD Simulation
Two-photon Laser Testing
Observed Results
Heavy ion and neutron testing on both silicon and silicon carbide MOSFETs also verified three distinct operating regions for a constant gate-to-source voltage of zero with varying LET values and drain-to-source voltages. Beyond a certain threshold, however, there is leakage current induced by radioactive particle flow in the device. Relative location of the three operating regions of a power MOSFET in sufficiently high LET radiation to cause increased drain to source leakage current and also BEE.
All devices tested are rated to support a drain-to-source voltage of 1200 V, but fail anywhere from 1100 V to 500 V based on the LET value. The radiation-induced leakage current has been shown to increase with respect to LET than with respect to total fluence, with some saturation occurring with respect to both variables. Since radiation-induced leakage breakdown, SEB, and SEGR are all destructive events, the development of a nondestructive alternative for experimentation is desirable.
Without the impact ionization models, an ionizing particle does not generate charge carriers in the simulation calculations.
Summary
With the Sentaurus model shock ionization turned off, no SEB occurs at a bias of 900V and a LET of 10, but with shock ionization turned on in the simulation, a SEB occurs in the same test environment. It boasts a higher breakdown field and thermal conductivity than silicon, allowing devices with similar breakdown voltages, current values and on-state resistances to be smaller in SiC than in silicon [14]. Specifically for SEBs in silicon, the defects are associated with a parasitic bipolar junction transistor (BJT) inherent in the structure of conventional vertical double-diffused metal oxide semiconductor (VDMOS) power FETs, as shown in Fig.
Further information on the structure and function of VDMOSFETs can be found in "Advanced Power MOSFET Concepts" by B. Evidence showing the effect of BJT parasitics on SEB in silicon is reinforced using back absorption testing with two-photon laser with burn protection. circuits to map the regions where failure is most likely to occur [8], [9]. Charge collection distributions isolate two distinct mechanisms, one resulting in proportional bias charge collection and one resulting in incremental amplification of the bias charge.
The latter is assumed in the work to be the parasitic bipolar gain associated with BEE in silicon power MOSFETs and inherent to the vertical. 20], technology computer-aided design (TCAD) simulations show that a parasitic bipolar effect can be an element of the SEB process in SiC MOSFETs using structures modeled after the device used in this work. It has been shown that SEB can be induced in SiC power diodes using TPA, and that the ability to SEB using TPA is dependent on diode reverse bias and laser focus location within a device under test (DUT) [10].
In this work, we investigate the charge collection induced in SiC MOSFETs and SiC power diodes in an attempt to explain similarities in their SEB response with respect to ion LET and bias voltage. The tests are performed using the two-photon laser technique through the back of SiC MOSFETs of 1200 V devices to produce non-catastrophic transients. For comparison, 1200 V SiC power diodes from the same manufacturer and technology are also tested.
The similarity of diodes to MOSFETs allows isolation of specific MOSFET mechanisms from the results. An explanation of the results is provided, as well as a discussion comparing these results with simulated and experimental results of previous work using other radiation sources.
Experimental Conditions
- Sample Devices
- Device Preparation
- Two-Photon Absorption Technique for SiC Devices
- Printed Circuit
The stripes are repeated with an increase of approx. 10 µm, determined by optical examination of the metal layers. The primary differences between the two are the lack of the gate and source structures in the diode and a hexagonal repeating geometry in the diode compared to the striped geometry in the MOSFET. Other device characteristics, including the dimensions of the hexagonal repeat geometry and overlay composition, are not available from the manufacturer and cannot be distinguished optically due to the uniform metal layer on the top side.
The highlighted cross-sectional region covers one of the parasitic bipolar transistors inherent in the device structure and known to play a fundamental role in the occurrence of SEB in Si and SiC vertical power MOSFETs. The hole is sized to expose approximately 30% of the backside, which results in negligible modification of the bias electric fields compared to an unmodified cover [9]. Gold bonding wires connect the gate and source/body contacts to the package pins, and the exposed cap and bond wires were then coated in HumiSeal 1A33 and allowed to cure to ensure safe device operation at bias over 100 V [24].
The drain contact is on the back of the device and is bonded directly to a package contact using silver epoxy, effectively re-metalizing part of the drain. The photodiode is used to measure the pulse-to-pulse variation of the laser energy using the same oscilloscope as the amplifier output. The voltage generated by the photodiode has not been quantified with energy values at the laser wavelength used, but the pulse energy is estimated to be in the order of nanojoules based on the efficiency of the photodiode.
Transients caused by laser pulses are isolated from noise by triggering the oscilloscope on pulses of the photodiode signal, shown in Fig. The response to pulsed TPA was studied as a function of bias and position of the laser spot. The location of the laser focus is recorded for each laser pulse and resulting oscilloscope output trace.
The location of the Z=0 axis was set at the SiC-metal interface of each device by finding the depth of focus of the laser with the most concentrated reflections from the metal as viewed through the rear camera. This method produced results within a few microns of the actual SiC-metal interface, an error that occurs when comparing results from multiple devices, as discussed later.
Experimental Results
We achieve this by comparing the response of the diode to the MOSFET (described below). The diode structure (including the metal) is most similar to the MOSFET. The distribution and amplitude of the collected charge in the diode is very similar in both distribution and amplitude to that of the MOSFET's trough.
As previously discussed, charge collection in the MOSFET structure was considered in two regions: below the source and below the gate. The laser is focused on the interface of the SiC and the adjacent material, which corresponds to a Z position of zero in the experimental results. Due to significant absorption of light in the polysilicon, <1% of the light transmitted through the SiC/polysilicon interface will return to the SiC region after reflection from the metal contact.
The simulated spatial distribution of optically generated carriers in the SiC layer is shown in Figure. In accordance with the above discussion, the generation of optical carriers in the source region is larger than in the gate region. 5b, the charge collection in the neck region under the gate is more than double the charge collection in the source and the body at the SiC-metal interface.
While not directly integrated with the TCAD simulations, the optical simulations show that the increased charge accumulation in the neck region is not due to enhanced optical generation from interfacial reflections. At lower biases, the differences in the depth of the depletion region present in both the diode and the MOSFET explain the variation in charge collection with diode bias (green curve), as seen in Fig. The amount of charge collected in the diode determines the fraction of charge collected in the MOSFET due to carrier generation in the epi-body depletion region.
Rather than a peak charge collection centered in each channel with a slight drop in charge collection in the middle of the neck between channels, the distributions around both channels are inevitable. At higher bias voltages, the bipolar transistor is turned on by the collected-charge induced voltage in the channel. Since the charge is deposited closer to the surface of the device in TCAD simulations, there is minimal influence of bias on accumulated charge in the diode.
Positionally, bipolar amplification results in a peak in charge collection when the charge generated in the channel is maximized for the MOSFET, while the diode has roughly constant charge collection at any carrier deposition location.
