System Design from Tiny Biosensors to Giant Arrays

20 2.12 Design parameters of the coupled bridge as a function of the inner core. diameter and number of wraps of a single coil. a) peak converter gain, (b) self and mutual inductance, (c) gain ratio, (d) SRF. 113 3.88 Selection of element groups for phase array calibration/focusing:. a) half of the array elements and (b) a quarter of the array elements.

NOMENCLATURE

INTRODUCTION

The thesis organization is as follows: the first chapter studies the underlying physics of inductance displacement sensors as a special case of the broader family of magnetic energy deviation sensors. First, an analysis of the economics of solar space power is presented and its implications discussed.

ANALYSIS AND DESIGN OF MAGNETIC ENERGY-DEVIATION SENSORS

Magnetic Susceptibility Sensors

It is worth noting that the stored magnetic energy due to a magnetic particle in space depends only on 𝑴(𝒓), the magnetic polarization and 𝑩0(𝒓) within𝑉𝑝. This result can be written in terms of 𝜒in the magnetic energy density of the undisturbed system, 𝑢𝐵0=|𝐵0|2/2𝜇0, as

Figure 2.2: Magnetic bead with volume 𝑉 𝑝 and susceptibility 𝜒 in a space 𝑉 0 with an unperturbed magnetic energy density of 𝑢 𝐵 0 = 𝐵 2

A Survey of Integrated Magnetic Biosensors

Therefore, 𝑢𝐵 ∝ 𝐼2 and the inductance shift in (2.13) is independent of the excitation current to the first order. An imbalance causes a deviation from the rest point of the amplifier and can thus be detected.

Figure 2.4: An oscillator circuit (a) with and (b) without a magnetic perturbation in the inductor core.

Coupled Inductive Bridge Sensors Transducer gainTransducer gain

The next section will describe a new bridge architecture that takes advantage of the mutual coupling of two coupled inductors to reduce its size while maintaining a matched frequency response. If the bridge is excited by a differential input and drives a matched load, the 𝑉𝑐-dependent part of the output can be neglected because it is multiplied by the perturbation terms only.

V out,p V out,n

It is important to note that unlike the approach in [22], Δ𝐿1 and Δ𝐿2 are not assumed to be equal.

V out,p

V out,n

First, a perturbation of the coupled core produces a differential inductance shift equal to the shift that the same perturbation would have produced if it had been placed on the surface of a single inductor composed of the series-connected core coils 𝐿𝑠𝑒𝑟 = 2(𝐿 + 𝑀). Input and output impedances are important to the design of the bridge excitation and receiver circuits and are estimated by approximating the bridge outputs as open circuits.

V tIt

The other fundamental source of noise is the excitation signal, which propagates to the output and is not necessarily ideal. These propagate to the output identical to (2.24), so the output noise due to each excitation source. where ± is added to determine whether we applied the source noise at the positive or negative input.

M BMA

Assuming that the thermal noise of all the inductors is uncorrelated, the total output noise due to the bridge inductors is,𝑒𝑛,𝑜𝑢𝑡|𝐿 ,𝑡 𝑜𝑡,. 2.32). 𝐻 𝑧, the thermal noise of the sensor is in most cases insignificant compared to the receiver's input-referenced noise.

C pCm

A Coupled Inductive Bridge - Proof-of-Concept Design

The minimum transducer gain is defined on the sensor surface in the center of the core. Next, the spatial transducer gain profile of the inductively coupled sensor was characterized (Fig. 2.22).

Figure 2.11: Top: complex frequency response of two types of magnetic bead [9].

Conclusions

Second, the transducer gain was already shown to decrease by about 0.25dB/𝜇m with height (Fig. 2.23) above it, so if the beads are not flush with the chip surface, a significant loss is expected. Finally, measurements are made at RF, where |𝜒| can be lower than its DC values ​​(Fig. 2.11).

Figure 2.25: Exemplary system response to different amounts of 4.5 𝜇 m iron-oxide beads.

CALTECH’S SPACE SOLAR POWER PROJECT 1

Introduction

A collaboration of researchers in the fields of electronics, photovoltaics and lightweight space structures has been working since 2015 to develop new architectures, structures and circuits to enable feasible space-based power transfer. The following sections will describe the space solar power system with an emphasis on the electrical functionality.

Figure 3.1: Glaser’s original patent drawing of a solar power satellite.

System Overview Cost PerspectiveCost Perspective

A crucial decision in the orbital design of the space solar constellation is the choice of orbit altitude. Given 𝜅 and 𝑀𝐺 𝐸 𝑂, and the mass of the space vehicle, we can calculate the number of space vehicles of mass 𝑚𝑆𝑉 that a given launch vehicle can place in GEO, 𝑛𝑆𝑉. 3.11). Since both 𝑁𝑆𝑉 and 𝑁𝐿 are linearly dependent on 𝑃𝑔, the mass and surface area of ​​the space vehicle determine the slopes of the graphs of both quantities as functions of 𝑃𝑔.

Based on these relationships, we can estimate the cost of the space part of a SSP system.

Figure 3.2: Cost of expeditionary power. Both JP8 cost and the JP8 cost of transport to destination affect total cost in operation [40].

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System Level Design

The choice of the operating frequency is probably the most important design choice for the RF part of the SSP system. Interestingly, due to the quadratic dependence of the far-field region (Fraunhofer) on the aperture [42]. Increasing the number of ICs per unit area alleviates much of the thermal dissipation challenge as will be shown later.

An asymptotic estimate for the expected improvement over time of plaque weight was given in [40].

Figure 3.6: Achievable efficiency for given PER, quality factor, and number of output matching stages [55].

RFIC Design

Since the transmitter is a directional antenna array, the main lobe carries most of the current. Therefore, an area from which the RF power density is negligible can be well defined for the sake of the general public. Several versions of the RFIC were manufactured, and in the latest version, only two PAs were stacked on top of each other to improve channel-to-channel isolation and circuit stability, as shown in Fig.

A major challenge with this architecture is maintaining the timing accuracy of the reference signal in the distribution process.

Figure 3.23: A top-level schematic of the SSP RFIC.

Tx Channel

DLL PLL

CMUs, PAs,

ADCs, Bias

Phase Cal

Regulators, Temp Sens

Bandgap ref

These are due to periodic variations of the VCO control voltage that exist when the PLL is locked with a net-zero charge injection per cycle. cycle. The PLL also uses a pass-through switch to cancel the effect of the charge pump current mismatch as shown in Fig. A heat map of the output reference trace harmonic was plotted versus the digitally variable start and stop times of the pass-through circuit breaker (Fig. 3.47).

Such checks can be used in the future as a basis for digital calibration of desired reference levels.

Figure 3.33: Length variations due to (a) reference distribution routing and (b) output antenna traces.

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Tile-Level Integration and SSPP Demo

The system size can be quickly scaled by repeating the tile pattern on a large flexible laminate (Fig. 3.59). Although the RFIC could be assembled directly on the flexible PCB, this would cause significant stress on the soldered bumps, which could lead to mechanical failure. In addition, it will require very tight control of the flexible PCB metal traces, which can be expensive for large boards.

The small interface adds just a bit of stiffness to the flexible circuit and is helpful in extending the RFIC digital control lines and in converting the 50 Ω radiator transmission lines to exhibit the optimal 75 Ω impedance for the PA outputs.

Table 3.10: DLL performance comparison table This work JSSC

Tile Unit CellScalable

Sheet

Main Board

Interposer RFIC

SPI bus RF outputs

RF match

System-scale Integration

Distributing a reference signal over large distances results in increased attenuation and noise due to clock line loading, as discussed in Section 3.4. This capability allows for distributed powering of the array, avoiding heavy and high current wiring. The initial assembly effort resulted in about 85% of the antennas being successfully reflown onto the main board, and the rest were reworked by hand.

While still not perfect, this made building the whole set much more manageable.

Figure 3.83: An assembled flexible phased array transmitter.

Raw Antenna Sheet

To demonstrate the beamforming and beam steering capabilities of the adaptive phased array, the array was calibrated in 5 different steering configurations using the previously described method. The scanning area in the near field region limits the measurement to 14 degrees in elevation and 40 degrees in azimuth in the far field, with the effects of non-physical transformation occurring at the extreme limits of the width of view. This power estimate is pessimistic because it assumes that the initial location of the probe was actually at the main lobe maximum and neglects losses due to the nonisotropic probe pattern.

The array is then re-focused to correct for the aberrations introduced into the pattern by the shape change and to find the optimal phases to recreate a wide main lobe.

Figure 3.86: Antenna sheet assembly. (a) Schematic description and (b) a demon- demon-stration of the assembly process.

SYNCHRONIZING RF PHASED ARRAYS WITH LIGHT 1

Introduction

However, this architecture is unacceptable for many commercial applications, in which the economics of the system determine its feasibility. Indirect frequency distribution at low frequency is simple at the board level and allows large parts of the systems to be implemented on a low-cost substrate. Frequency generation at those frequencies, usually on the order of 10s of MHz, is simple and accurate through the use of quartz crystals.

However, the clock distribution scheme becomes difficult with the increase in array size, loading the clock source unacceptably.

Theoretical Background

For an output power of 𝑃𝑐 ℎ𝑖 𝑝 delivered to 𝑁 RFIC PD with conversion efficiency𝜂𝑃 𝐷, the power dissipation associated with the clock division is equal. There are two length quantities that must be calculated to estimate clock power dissipation for the different methods, as shown in Figure 4.4: the total length of traces in an H-tree, and the trace length from the clock source to a single chip. For 2×2 antennas per chip, there is a distance of 𝜆 between the chips and a total side size of 𝑑 =𝜆 𝑁𝑠𝑖 𝑑𝑒. The trace length to each RFIC grows with N axis.

There is another subtlety that is crucial to understanding why an optical reference distribution is desirable.

Figure 4.1: High frequency clock distribution schemes: (a) RF based and (b) laser based.

Chip Design

The design process started with an estimate of the technology layer structure and doping (Fig. 4.7), and was followed by layout construction and simulation in a dedicated software tool [107] to estimate the PD current versus the input power and the parasitic frequency-dependent response, expressed mainly as shunt capacitance. The subsequent steps use a common-mode feedback amplifier to ensure the inverters operating point (Fig. 4.12). The simulated single-ended output voltage of the chip input chain is illustrated in fig.

Although more sophisticated topologies exist [110], this amplifier is robust with a reasonable output power and drain efficiency (12.5dBm and 28%, respectively), and allows it to be operated against backlash if we also have a non-uniform want to demonstrate phased array operation. 4.21 illustrates the power amplifier circuits and Fig. 4.22 shows the simulated output swing and small signal gain.

Figure 4.6: Small signal model of a CMOS PD (recreated from [106]).

BIBLIOGRAPHY

Lee, “Simple Exact Expressions for Planar Spiral Inductances,” IEEE Journal of Solid- State Circuits, vol. Hajimiri, “A scalable 6 to 18 ghz dual-band phased-array receiver in cmos,” IEEE Journal of Solid-State Circuits, vol. Kim, “A 250-MHz-2-GHz wide-range locked-delay loop,” IEEE Journal of Solid-State Circuits, vol.

Cho, “A dual locked-delay loop using multiple voltage-controlled delay lines,” IEEE Journal of Solid-State Circuits , vol.