Abstract
The rapid development of medical imaging has transformed the modern healthcare.
These high resolution images occupy enormous memory space for storage and require high channel bandwidth for transmission. The JPEG 2000 based image compression system is adopted to compress an image without degrading the image quality. A completely hardware based JPEG 2000 image compression / decompression system is in the process of development at VLSI CAD Laboratory, IIT Kharagpur and the author has developed the image decoding modules which form a part of the overall sys- tem. The Discrete Wavelet Transform (DWT)/Inverse Discrete Wavelet Transform (IDWT) and embedded block coding/decoding algorithms are the essential compo- nents of the JPEG 2000 encoder /decoder system. The computational complexity of the block coding/decoding algorithm is more and consumes 53% of the total com- putation time. The hardware accelerator for Block Coder/Decoder is essential to speed up the overall encoding/decoding process. For this purpose, a high throughput pass parallel Block Decoder (BD) architecture is proposed and implemented. The BD can decode an average of 1.4 bits per clock cycle. To avoid unnecessary read and write data in the state memories, an efficient memory arrangement technique is proposed. In pass parallel mode, registers and states of the Arithmetic Decoder (AD) are initialized at the beginning of each coding pass and take few clock cycles.
This work presents a selective byte input technique which can load a single or double byte in a clock cycle to avoid stalling during initialization. The Figure of Merit, which is defined as the ratio of throughput and hardware cost, of the proposed ar- chitecture is more than that of the available BD architectures. A VLSI architecture for lifting based combined lossy (9/7) and lossless (5/3) IDWT is presented, which has critical path of an adder delay (Ta). The on-chip memory requirements of the proposed IDWT architecture are 5N and 3N (both having word length of 17 bits) respectively for an N×N image, which are lower than that of the available line based architectures. Additionally, a dead-zone scalar dequantizer is adopted in this work to reconstruct the DWT coefficients at the lossy mode of image compression. The interface between BD and IDWT modules is a challenging job due to the differences in input data format of the two blocks. The proposed back-end system of the JPEG 2000 decoder integrate BD, dequantizer and IDWT modules in a single framework.
Keywords: JPEG 2000, Lifting-based IDWT, Block Decoder, Bit-Plane Decoder, MQ Decoder, Dequantizer, VLSI Architecture, FPGA.
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