Building a Fast SDRAM Controller with Ping Pong FIFO's for AHB Interface

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ISSN (Print): 2278-8948, Volume-2, Issue-5, 2013

62

Building a Fast SDRAM Controller with Ping Pong FIFO's for AHB Interface

Archana C. Sharma¹, Zoonubiya Ali² & Rahulkumar Kothimbire³

1&2ECE, DIMAT, Raipur, India

3Consumer Electronics, L G Electronics, Pune

E-mail : [email protected]¹, [email protected]², [email protected]³

Abstract - Fifty years of development have resulted in a spectacular increase in the performance of processors and an equally spectacular reduction in their cost in terms of latency. Today's issue is the speed of fetching data from memories is unable to cope up with speed of processors hence fast memory controllers are needed that eventually increases memory efficiency. Memory controller is responsible to match speed of processor and memory one and the other side, so as to enable seamless communication. In this paper we are proposing and building a memory controller which is specifically targeted for SDRAM and is designed compatible with Advanced High-performance Bus (AHB) which is a new generation of AMBA bus. We are specially selecting memory type SDRAM as SDRAM and DDR memories are mostly used in memory designs of embedded systems as it is boosted with high speed, burst access, pipelining, portability and proper command initialization. Synchronous DRAM (SDRAM) is a synchronous interface type of DRAM means here every memory command activity occurs for only change in clock signal.

The objective of thesis is to design a controller that can be used to implement both write and read operation with SDRAM controller based on read FIFO'ing , ping-pong technique and read update logic. It also can be used to reduce time delay of controller, to improve the high performance using AMBA AHB bus.

Keywords - AHB , Memory Controller, AHB bus, System-on- chip, SDRAM , FIFO, Double Buffering, Xilinx ISE.

I. INTRODUCTION

Our aim is to design two way cable networked SoC, that is SDRAM controller connected by AMBA (Advanced Microcontroller Bus Architecture) which has been widely adopted as on-chip bus architecture for ARM processors. The first AMBA buses introduced were the ARM System Bus (ASB) and the ARM Peripheral Bus (APB). Later ARM High Performance

Bus (AHB) was introduced. AHB provides higher data throughput than ASB because it is based on a centralized multiplexed bus scheme rather than the ASB bidirectional bus design and it runs at higher clock speeds and to support widths of 64 and 128 bits. AHB features includes: Highest bandwidth operation , Pipelined operation, burst transfers, Multiple Bus masters, split transactions, single-cycle bus master handover, single-clock edge operation, non-tri-state implementation and wider data bus configurations(64/128 bits).

Fig.1 : AMBA based microcontroller with classified bus

AMBA AHB AMBA ASB AMBA APB

High performance Multiple masters Pipelining Burst operation Split transaction

High performance Pipelining Multiple masters

Low power Simple interface Many peripheral Latched Address Latched control

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63 II. OBJECTIVEOFTHEWORK

AHB matches bandwidth requirements and responding speed requirements for SDRAM. By analyzing the multiple accesses from the modules and the SDRAM specifications such as its accessing delay, we take both sides into consideration. On side 1, we use bank closing control. On side 2, the controller employs two data write FIFO to reduce the data access awaiting time, and uses 2 read FIFO to decrease the CAS delay time when reading data from SDRAM.

The motivation towards this project is as follows:

1. To obtain fast and effective communication in modern large memory system with different data write and read operation of controller.

2. To reduce the time delay of controller and to increase the high performance of controller using AHB bus.

3. To make Controller is reconfigurable and scalable.

The objective of thesis is to design a controller that can be used to implement both write and read operation with SDRAM controller based on read FIFO'ing and ping-pong technique. And it also can be used to reduce time delay of controller, to improve the high performance using AMBA AHB bus.

III. ADVANCEHIGHPERFORMANCEBUS INTERFACE

AHB is a new generation of AMBA bus which is intended to address the requirements of high- performance synthesizable designs. It is a high- performance system bus that supports multiple bus masters and provides high-bandwidth operation.

Bridging between this higher level of bus and the current ASB/APB can be done efficiently to ensure that any existing designs can be easily integrated. An AMBA AHB design may contain one or more bus masters, typically a system would contain at least the processor and test interface. However, it would also be common for a Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus masters.

Fig. 2 : AHB Slave Interface Signal Description

1) HCLK Bus: Clock source: This clock times all bus transfers. All signal timings are related to the rising edge of HCLK.

2) HRESETn Reset Source: The bus reset signal is active LOW and is used to reset the system and the bus. This is an active LOW signal.

3) HADDR [31:0] (Address bus) Master: The 32-bit system addresses bus.

4) HTRANS [1:0] (Transfer type) Master: Indicates the type of the current transfer, which can be IDLE or BUSY.

5) HWRITE (Transfer direction) Master: When HIGH this signal indicates a write transfer and LOW as read transfer.

6) HBURST [2:0] (Burst type) Master: Four, eight and sixteen beat bursts are supported.

7) HWDATA [31:0] (Write data bus) Master: The write data bus is used to transfer data from the master to the bus slaves during write operations. A minimum data bus width of 32 bits is recommended.

8) HSELx (Slave select) Decoder: Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave.

9) HRDATA [31:0] (Read data bus) Slave: The read data bus is used to transfer data from bus slaves to the bus master during read operations. A minimum data bus width of 32 bits is recommended.

However, this may easily be extended to allow for higher bandwidth operation.

10) HREADY (Transfer done) Slave: When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal may be driven LOW to extend a transfer.

Note: Slaves on the bus require HREADY as both an input and an output signal

11) HRESP [1:0] (Transfer response) Slave: The transfer response provides additional information on the status of a transfer. Four different responses are provided but for our design we consider OKAY and ERROR as for one master.

A. Basic Transfer

An AHB transfer consists of two distinct sections:

1. The address phase, which lasts only a single cycle.

2. The data phase, which may require several cycles.

This is achieved using the READY signal.

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64 In a simple transfer with no wait states the master drives the address and control signals onto the bus after the rising edge of HCLK. The slave then samples the address and control information on the next rising edge of the clock.

Fig. 3: Basic AHB Transfer

IV. SYNCHRONOUSDYNAMICRANDOM ACCESSMEMORY(SDRAM):

Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus enabling higher speed. The SDRAM controller is capable of either 16-bit or 32-bit data path, and supports byte, half- word and word access. Bursts can be used for both write and read access.

Fig. 4 : SDRAM interface signals and state machine

 SDRAM signals: RASb Row Address Strobe:

Along with /CAS and /WE, this selects one among different commands. It is active low signal which works for row address in the memory.

 CASb Column Address Strobe: Along with /RAS and /WE, this selects one of 8 commands. It is active low signal which works for column address in the memory.

 WEb Write enable: Along with /RAS and /CAS, this selects one among different commands. This generally distinguishes read-like commands from write-like commands. All the above are command bits.

TABLEI: SDRAM COMMAND WITH STROBE SELECT Function Cs RA

Sb

CASb

WEb Add

Active L L H H Row

Read L H L H Col

Write L H L L Col

Precharg

e L L H

L Row

 DQ Data lines: This is a bi-directional bus signal on which either a data read or a data write operation is taken at a time. both operations cannot be taken in parallel. This bidirectional bus carries data to and from the memory.

 DQM Data Mask: When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. The masked data remains unchanged and unmasked data is what a master accessed for either a read or a write operation.

V. SYSTEMDESIGNMODULE

Fig. 5: System module

Since the processor is faster than the memory, it is illogical to make the processor wait till each command is executed for it to give the next command. So the

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65 controller has to have some kind of storage as given in figure above, so that it can buffer multiple requests from the AHB slave interface while the processor continues with other work.

We used FIFO to store the Read/Write commands coming from processors/user side along with corresponding write data and included a search engine to search recently read/write data inside the FIFO in order reduce the clock cycles of fetching data from SDRAM.

Fig. 6: Flow of control in SDRAM Controller System A. Operation of SDRAM controller

Only one open row in an active bank can be accessed. An ACTIVE command can open a row and make active the particular row in the memory. A PRECHARGE command issued to memory can set the SDRAM to idle state, i.e. closing the open row in this memory. If every time after accessing a row AUTOPRECHARGE command is performed, and the next access is actually involving the same row of the same bank, an ACTIVE command needs to be applied again in order to access last open row.

Fig.7: Proposed architecture of SDRAM controller As it is known that time needed between ACTIVE and READ/WRITE commands has to be fulfilled. In a successive period of time a program probably only accesses a small part of continuous address space. So that it is not necessary to issue an AUTO-PRECHARGE command after every read/write access without judging

if there’s any need. If the current access is for an open row in an active bank, the READ or WRITE command is directly issued to the SDRAM, the ACTIVE and READ or WRITE commands.

When the auto-refresh is required, all the active banks will be inactivated by applying PRECHARGE ALL command as auto-refresh can only be issued when the whole SDRAM is in idle state. In this way, the overhead caused by frequently opening and closing the SDRAM banks can be decreased.

The memory controller basically consist of three main sub parts, they are

1) 2 Read and 2 write FIFOs 2) Command generator

3) Command scheduler Read FIFO

It is known that, SDRAM cannot finish the data access in a single cycle. So we need some strategies to decrease the responding time. We analyzed our application and found that if the SDRAM is accessed in the single mode, the needing data is available at least after 2 cycles Plus time consumed by the latching in the bus interface part and the PRECHARGE command, in fact, it is more than 2 cycles. To support the fast response time, burst mode access and read FIFO'ing techniques need to be used whenever possible.

When AHB bus needs to read data, see if data is already in read FIFO by only checking if the current accessing address is in the range of either of the read FIFO and if the corresponding bit in the corresponding Valid-Vector is valid. The Valid-Vector is used to mark if the data stored in data FIFO is valid. Valid-Vector works like tags for a cache.

Every read FIFO is only as big as the capacity of a SDRAM burst, so that Valid-Vector is only a several bit vector. If the needed data is in read FIFO, data can be directly read from them, otherwise, a READ command is needed issuing to SDRAM. After a preset number of clock cycles, the data is available on the output latches of the SDRAM for reading, and data is delivered to AHB bus and written to one of the read FIFO at the same time. The whole burst access data will be loaded in read FIFO.

In this way, we implemented prefetching.

According to the local principles of programs, the next read access is possibly a successive address to the current one. So the next data can be read from read FIFO, which can fasten the responding speed. In order to reduce the complexity of implementing read FIFO, data from SDRAM are stored in read FIFO 0 and read FIFO1 in turn.

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66 B. Double Buffering or Writing in Ping-Ponging

As it is described about the AHB, in order to reduce the responding time to write access, write FIFO are used to pack and align the data when the AHB bus data transfer size does not match the SDRAM data bus width. Based on our previous research on FPGA designs, we didn’t use only one write FIFO, instead, we use 2 FIFO. It is well known that ping-ponging can reduce or eliminate the mismatch effects between 2 different modules which are operating at different speeds.

By utilizing ping-ponging between the two write FIFO, part of the time writing one FIFO and part of the time moving data from another FIFO to off chip SDRAM can be overlapped.

If write FIFO 0 is not empty and write FIFO 1 is being written by AHB bus, move FIFO 0’s data to SDRAM and this FIFO will be in the progress of moving until all data is moved to SDRAM, vice versa.

This is the ping-ponging technique we used between write FIFO 0 and write FIFO 1.

The flow of moving data from FIFO to SDRAM is as follows:

Fig. 8: Data Flow in Double Bufering

1) If write FIFO 0 is empty, data will be written to write FIFO 0.

2) Else if write FIFO 1 is in the progress of AHB writing and write If write FIFO 0 is being written by AHB bus and write FIFO 1 is not empty, move FIFO 1’s data to SDRAM and if FIFO 0 is not empty, move FIFO 0’s data to SDRAM.

3) This flow explains how the ping-ponging can make the time writing FIFO and writing SDRAM overlap.

The description of operations about AHB bus writing FIFO is as follows:

a) If write FIFO 0 is empty, data will be written to write FIFO 0.

b) Else if write FIFO 0 is not empty or in the progress of moving its data to SDRAM and if write FIFO 1 is empty, data will be written to write FIFO 1.

c) Else make the AHB bus hold the bus signals until

one of the FIFO is empty.

C. Read Update Logic

One of the novel features of this controller is read update logic. When the controller encounters a read command at the head of the FIFO queue, it takes this command and searches the FIFO to see if the required data is already in the FIFO. This search is carried out in parallel and all the FIFO locations are searched in one clock cycle. Hence the searching time is not dependent on the depth of the FIFO but at the cost of hardware overhead. Once the data is found in the FIFO, which was the result of a previous operation, it is directly routed to the output. Hence saving the time and burden of fetching it from the DRAM memory. If the data is not found in the FIFO then the controller executes the request on the memory as usual.

Thus if the data is found internally then we save a lot of clock cycles, but even if the data is not found internally then we just lose one clock cycle.

Fig. 9: Search Logic used by controller TABLE II: PROBABLE CONDITIONS FOR

COMMAND GENERATOR Scenario1:

Y=null ROW EMPTY

Scenario2:

X==Y

ROW HIT

Scenario3:

X!=Y ROW CONFLICT

ACT X RD/WR X PRE Y

RD/WR ACT X

RD/WR X Where X=Requested address by master Y=Current address in the activated row buffer

1) ROW EMPTY (RE): For any read/write operation check for the row buffer status, if f the row buffer is empty then directly go for activating the row buffer by the command ACT from the command generation and

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67 then perform the requested read or write operation on the row buffer by giving the RD/WR command.

2) ROW HIT (RH): For any read/write operation check for the row buffer status, if f the requested address corresponds the same row which is already activated in the row buffer for any previous transfer, then directly perform the requested read or write operation on the row buffer by giving the RD/WR command.

3) ROW CONFLICT (RC): For any read/write operation check for the row buffer status, if the requested address differs from the row which is already activated in the row buffer for any previous transfer, then precharge the existing row in the row buffer by giving the PRE command and then activate the requested address row by the ACT command and perform the requested read or write operation on the row buffer by giving the RD/WR command.

Fig. 10: Command generator state machine

In state machine, at every state for different operation we are storing the commands The first condition is , if the present state is a read there exist four combinations of operations that has to be taken,

1. RD to RD in row hit scenario 2. RD to RD in row conflict scenario 3.RD to WR in row hit scenario 4.RD to WR in row conflict scenario

The second condition is, if the present state is a write there exist four combinations of operations that has to be taken,

1. WR to WR in row hit scenario 2.WR to WR in row conflict scenario 3.WR to RD in row hit scenario 4.WR to RD in row conflict scenario

D. Command scheduler

The command scheduler gives the timing analysis for all the commands which are generated from the command generator.

TABLE III: RELEVANT TIMING PARAMETERS FOR THIS DESIGN

Description Parameter Min

Cycles IDLE to ACT command

delay TRESRAS 20

ACT TO RD command

delay TRASRD 7

ACT to WR command delay TRASWR 8

RD to PRECHARGE

command delay TRDPR 12

WR to PRECHARGE

command delay TWRPR 15

RD to WR command delay TRDWR 6 WR to RD command delay TWRRD 9 RD to RD command delay TRDRD 4 WR to WR command delay TWRWR 8 PRECHARGE to ACT

command delay TPRRAS 18

A parameter T is defined to every operation of the commands taking place as shown in the figure and the relevant timing parameters which are described for our memory is shown in table.

VI. SIMULATIONRESULTSPROBABLE CONDITIONSFORCOMMANDGENERATOR

Fig. 11: SDRAM memory simulation

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Fig. 12.AHB- Memory controller Original

Fig. 13: AHB- Memory controller Updated

VII. SYNTHESISREPORT

Fig.14: SDRAM memory RTL schematic

Fig. 15: SDRAM Controller RTL schematic (Without updated logic)

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Fig.16: SDRAM controller RTL schematic (With updated logic)

A. Without updated memory controller results 1) Timing Summary

Minimum period: 10.832ns

(Maximum Frequency: 92.319MHz)

Minimum input arrival time before clock: 9.902ns Maximum output required time after clock: 12.479ns Maximum combinational path delay : 11.460ns Timing Detail

All values displayed in nanoseconds (ns) 2) Timing constraint

Default period analysis for Clock 'clk_count_261' Clock period: 10.832ns (frequency: 92.319MHz) Total number of paths / destination ports: 15992 / 461 Delay: 10.832ns (Levels of Logic = 7

Source: HADDR_9 (FF) Destination: write_count_0 (FF) Source Clock: clk_count_261 rising Destination Clock: clk_count_261rising B. Updated memory controller results 1) Timing Summary

Minimum period: 8.743ns

Maximum Frequency: 114.383MHz

Minimum input arrival time before clock: 6.914ns

Maximum output required time after clock: 10.075ns Maximum combinational path delay: No path found Timing Detail

All values displayed in nanoseconds (ns) 2) Timing constraint

Default period analysis for Clock 'clk_count_261' Clock period: 8.743ns (frequency: 114.383MHz) Total number of paths / destination ports: 16101 / 1162 Delay: 8.743ns (Levels of Logic = 5)

Source: mc0/write_buf_write_pointer_1_1 (FF) Destination: mc0/write_addr_buf<1>_3_31 (FF) Source Clock: clk_count_261 rising

Destination Clock : clk_count_261 rising The results in table 4 are normalized according to those from the SDRAM controller described in this project. The frequency of the whole SoC got from ISE is 92 MHZ for the existing SDRAM controller and 114MHZ for the modified SDRAM controller we described in this project. We can see that our SDRAM controller has made a significant decrease of the total execution time of the application program.

VIII.CONCLUSION

This paper presents an illustrative case of AMBA AHB bus that can be model SDRAM Controller interface. The proposed Controller is simulated and synthesized for performance For a master that hands its request to interface, transaction is completed at the moment the request in handover to controller and bus is free.

Thus not only the SDRAM memory is getting efficient but AHB bus utilization also enhances as per our design. By utilizing four FIFO with controller two operation i.e..double buffering in ping-pong fashion and Read update logic is evaluated that yields in reducing the execution time by 86% and thus improving throughput and efficiency of both AHB interface and SDRAM memory implementing a faster SDRAM controller for AHB interface. Double buffering is used in a transmission that contains two separate buffers, that altogether have 8 locations to store 4 data and four memory location that are recently accessed. While one buffer is receiving new transmission information the other buffer is deleting the previous transmission.

Also with read updating every time requested data is searched in the four address before any reading.

Parallel data processing in each pair of FIFO costs not

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70 for FIFO depth but for hardware overhead. Our SDRAM controller is modified herewith two reading and two writing at a same time. The FIFO's are used to change the data path from AHB to SDRAM and flow of command generator operation. As without FIFO the command generator directly communicates with memory but in updated logic command generator and scheduler use FIFO's for scheduling and queuing the commands in between.

IX. FUTURESCOPEANDADVANTAGES 1) Consumes less power. That is why it is specially

suited for notebook computers.

2) The high performance AMBA AHB interface is used for the speed compatibility between master and the memory.

3) Memory access time is getting reduced because of the latency reduced by 91.66% after the design is used.

4) It has the capacity to transfer data 64 bits at a time at 100 MHz bus frequency.

5) It also supports burst transfer of the data, masking.

6) Chip achieves less area as DRAMs has only one transistor and one capacitor.

X. REFERENCES

[1] Hu Yueli,Yang Ben "Building an AMBA AHB compliant Memory Controller” in 2011.

[2] Construct High-Speed SDRAM Memory Controller Using Multiple FIFO's for AHB Memory Slave Interface A. C. Sharma Volume 3, Issue 3, March 2013..

[3] “PrimeCell AHB SRAM/NOR Memory Controller”, Technical Reference Manual, ARM Inc.

[4] Micron Technology Inc.Synchronous DRAM Data Sheet, 2001.

[5] “Memory Controllers for Real-Time Embedded systems” BennyAkesson Kees Goossens vol. 3, no. 3, pp. 75–77, Mar1999..

[6] Double Data Rate (DDR) SDRAM Specification, JEDEC STANDARD, JESD79E, May 2005 [7] ARM. “AMBA Open Specifications”

http://www.arm.com/products/system- ip/amba/amba-openspecifications.php

[8] http://infocenter.arm.com/help/topic/com.arm.doc [9] Samir Palnitkar, Pearson 2nd edition “Verilog HDL, A Guide to Digital Design and Synthesis

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