Design of Low Power Reversible Decoder using GDI Technique

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International Journal of Advance Electrical and Electronics Engineering (IJAEEE)

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Design of Low Power Reversible Decoder using GDI Technique

1Majety Naveen Kumar & ²A.V.M Manikandan

1,2Department of Electronics and Communications Engineering, SRM University, Chennai, India Email : ¹[email protected], ²[email protected]

Abstract - Reversible logic has very important role in recent times and it is used in reducing power consumption in digital logic design. It consumes less power by regaining the bit loss from its unique input–output mapping. Gate Diffusion Input (GDI) is a technique of low-power digital circuit design, this technique reduces the power consumption, propagation delay, and area of digital circuits by maintaining the complexity very low of logic design. In this paper, 2 types of reversible decoders using GDI is proposed which can provide active high and low outputs. 1^st type of Reversible decoder uses Feynman and Fredkin Gate and 2^nd type of reversible decoder uses HL and Fredkin Gate. The simulations are done in H-Spice using 90nm technology and a comparison has been done between existing reversible decoder using conventional CMOS and proposed reversible decoder using GDI.

Keywords—Reversible logic, CMOS, Digital low power, Delay, GDI, Reversible Decoder, Feynman Gate, Fredkin Gate, HL Gate.

I. INTRODUCTION

Today’s advancement in level of integration and fabrication process has getting better logic circuits and energy loss has also been dramatically reduced.

According to Landauer principle [1], in every logic computation a bit of information loss generates kTln2 joules of heat energy where k is the Boltzmann constant of 1.38 × 10^-23 J/K and T is the absolute temperature of the environment. Reversible circuits are basically different from traditional irreversible ones. In reversible logic, no information is lost. Bennett [2] showed that zero energy dissipation would be possible if the network consists of reversible gates only. But the drawback is area will be increased compared to irreversible circuits even though Reversible Gates are much better than conventional CMOS [3].

A reversible circuit should have the following attributes [4]:

1. Garbage output should be as minimum as possible.

2. Number of reversible gate should be as minimum as possible.

3. Input lines that are either 0 or 1, known as constant input, should be as minimum as possible.

There are different types of styles logical design like,

Pass Transistor Logic (PTL): There are two basic problems [5] one is threshold drop across pass transistor results in slower operations of circuits and other problem is that there will be direct static path for power dissipation due to PMOS device in the inverter circuit is not fully turned off.

Transmission gate (TG): It solves the low logic level swing problem by using PMOS and NMOS Connected Complementary Pass-transistor Logic (CPL): The CPL suffers from static power consumption due to the low swing at the gates of the output inverters [6].

Double Pass-transistor Logic (DPL): Uses complementary transistors to keep full swing operation and reduce the dc power consumption. One disadvantage of DPL is the large area used due to the presence of pMOS transistors.

Gate Diffusion Technique (GDI) is a low power technique, which solves the most of problems mentioned above. The GDI approach allows implementation of a wide range of complex logic functions using only two transistors. This method is suitable for design of fast, low-power circuits, using a reduced number of transistors (as compared to CMOS and existing PTL techniques), while improving logic level swing and static power characteristics and allowing simple top- down design by using small cell library.

Fig.1. GDI basic cell

The GDI method is based on the use of a simple cell as shown in Fig. 1. At first look, the circuit reminds one of the standard CMOS inverter, but there are some important differences.

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1) The GDI cell contains three inputs: G (common gate input of nMOS and pMOS), P (input to the source/drain of pMOS), and N (input to the source/drain of nMOS) [7].

2) Bulks of both nMOS and pMOS are connected to N or P (respectively), so it can be arbitrarily biased at contrast with a CMOS inverter [7].

II. BACK GROUND AND BASIC CONCEPTS

Basic Gates like AND Gate, OR Gate, XOR Gate designed by using GDI is very useful in designing reversible gates. The major design issue in GDI is we have to choose always a proper W/L Ratios and Vdd

otherwise the output will distorted sometimes output will be wrong due to improper choosing of W/L Ratio.

1. AND GATE

AND Gate in conventional CMOS has 6 transistors, but by using GDI structure it has only 2 transistors [7].

Fig.2. AND Gate 2. OR GATE

OR Gate [8] in conventional CMOS has 6 transistors, but by using GDI structure it has only 2 transistors [7].

Fig.3. OR Gate 3. XOR GATE

XOR Gate [7] in conventional CMOS has 12 transistors, but by using GDI structure it has only 4 transistors.

Fig.4. XOR Gate

III. PROPOSED REVERSIBLE GATES USING GDI

Proposed Reversible gates are FEYNMAN Gate (FG), FREDKIN Gate (FRG), HL Gate. These gates are designed by GDI structure so that there will be a large amount of power, transistors and delay reduction.

1. FEYNMAN GATE (FG)

The Feynman Gate which is a 2*2 gate and is also called as Controlled NOT and it is widely used for fan-out [4].

Fig.5. FEYNMAN Gate 2. FREDKIN GATE

It is also called Controlled Swap Gate (CSWAPG). It is a universal 3*3 gate, which means that any logical or arithmetic operation can be constructed totally by Fredkin gate. The Fredkin Gate is the three bit gate that swaps the last two bits if first bit is 1 [4].

Fig.6. FREDKIN Gate 3. HL GATE

It is 4*4 Reversible gate, mainly this gate is used for designing Reversible decoders [4].

Fig.7. HL Gate

TABLE –I: Comparison between Reversible Gates

Gate s

CMOS GDI %

Reduction in Power

& Area Power Transistor

Count Power Transistor Count FG 0.1

µw 12 27 nW 4 94.2% &

66.7%

FRG 0.9m

W 50 0.1m

W 18 88.8% &

72.3%

HL 9.4m

W 124 0.6m

W 52 92.1% &

58.2%

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IV. PROPOSED 2:4 REVERSIBLE DECODER USING GDI TECHNIQUE

There are two approaches to design 2:4 reversible decoders. One is by using Feynman gate and Fredkin gate, which produces one garbage output [8] and the other, by using HL gate, which produces no garbage output [8]. Fig 8 and 9 shows the two approaches.

Table-II provides the performance comparison of the conventional CMOS and proposed reversible decoder.

We can infer that GDI based reversible decoder is far better than the conventional CMOS reversible decoder in terms of power, no. of. transistors and delay.

Fig.8.Proposed 2:4 Reversible Decoder using Approach-1

Fig.9. Proposed 2:4 Reversible Decoder using Approach-II

Fig.10. Simulated waveform of proposed 2:4 approach-I

Fig.11. Simulated waveform of proposed 2:4 approach- II

TABLE –II: COMPARISON BETWEEN TWO DIFFERENT TYPES OF 2:4 REVERSIBLE DECODERS BY USING DIFFERENT TECHNIQUES

Logic

Style Parameters

2:4 Reversible Decoder Using FG &

FRG

2:4 Reversible Decoder Using HL Gate

CMOS

Power 3.2 mW 9.41 mW

Transistor Count 112 124

GDI

Transistor Count 40 52

% Reduction in Power 86.5% 92.1%

% Reduction in no. of

Transistors 64.2% 58%

Garbage Outputs 1 0

By using GDI based reversible decoder, the percentage of power reduction is about 90% due to no. of transitions in the circuit greatly reduced and no. of transistors reduction is about 60%. So the design complexity and critical path from input to output is greatly reduced by using GDI technique.

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V. PROPOSED 3:8 REVERSIBLE DECODER USING GDI TECHNIQUE

The proposed 3:8 GDI reversible decoder uses the proposed 2:4 GDI reversible decoder and cascade it with four Fredkin gates. This decoder can be easily generalized to m:2^m reversible decoder [9]. There are two approaches for the proposed design as shown in Fig 12 and 13. The 1^st approach of the proposed 3:8 GDI reversible decoder produces 2 garbage outputs [8], but the 2^nd approach produce, only 1 garbage output [8].

Fig.12. Proposed 3:8 Reversible Decoder using approach –I

Fig.13. Proposed 3:8 Reversible Decoder using approach –II

The comparison between proposed and existing 3:8 reversible decoder, is given in table –III. The proposed GDI based reversible decoder is far better than conventional CMOS Reversible decoder, with respect to parameters like Power, Transistors and Delay. Delay will be reduced by using GDI Technique because the critical path from input to output is reduced.

Fig.14. Simulated waveform of proposed 3:8 approach-I

Fig.15. Simulated waveform of proposed 3:8 approach- II

TABLE –III: COMPARISON OF DIFFERENT 3:8 REVERSIBLE DECODERS BY USING DIFFERENT TECHNIQUES

Logic

Style Parameters

3:8 Reversible Decoder Using FG &

FRG

3:8 Reversible Decoder Using HL Gate

CMOS

Transistor

Count 312 324

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GDI

Transistor

Count 112 124

% Reduction of Power 82.2% 83.48%

% Reduction of No. of

Transistors 64.1% 61.4%

Garbage Values 2 1

The proposed GDI based 3:8 Decoders about 80% of power reduction and about 65% of transistor count reduction as compared to the conventional decoder.

Thus the proposed design greatly improves over existing design in terms of power and no. of transistors.

VI

. CONCLUSION

Reversible Decoder of size 2:4 is presented in this paper and is extended to 3:8 Reversible Decoder. This 3:8 Reversible Decoder can be generalized to m:2^m Reversible Decoder. The proposed reversible decoders are implemented by using GDI technique. Comparisons between conventional CMOS and proposed decoders were carried out in table-II and table-III, showing that more than 80% of power had been reduced using proposed Technique and 60-65% of transistor count reduction has been obtained by using proposed technique. The proposed approach-I and approach-II is efficient in power reduction and in transistor reduction.

VII. REFERENCES

[1] R. Landauer, Irreversibility and heat generation in the computational process, IBM Journal of Research and Development 3 (1961) 183–191.

[2] C.H. Bennett, Logical reversibility of computation, IBM Journal of Research and Development (November) (1973) 525–532.

[3] B.Raghu kanth, B.Murali Krishna, M. Sridhar, V.G. Santhi Swaroop, “A distinguish between

reversible and conventional logic gates”, International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 2,Mar-Apr 2012, pp.148-151.

[4] Raghava Garipelly, P.Madhu Kiran, A.Santhos Kumar, “A Review on Reversible Logic Gates and their Implementation” International Journal of Emerging Technology and Advanced Engineering, ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 3, March 2013.

[5] W. Al-Assadi, A. P. Jayasumana, and Y. K.

Malaiya, “Pass-transistor logic design,” Int. J.

Electron., vol. 70, pp. 739–749, 1991.

[6] Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner, “Gate-Diffusion Input (GDI) – A Technique for Low Power Design of Digital Circuts: Analysis and Characterization” IEEE transactions on very large scale integration 2002 [7] Arkadiy Morgenshtein, Alexander Fish, and

Israel A. Wagner, “Gate-Diffusion Input (GDI):

A Power-Efficient Method for Digital Combinatorial Circuits” IEEE transactions on Very Large Scale Integration (VLSI) systems, vol. 10, no. 5, october 2002.

[8] Lafifa Jamal, Md. Masbaul Alam, Hafiz Md.

Hasan Babu, “An efficient approach to design a reversible control unit of a processor” Sustainable Computing: Informatics and Systems 3 (2013) 286– 294.

[9] Neeta Pandey, Nalin Dadhich, Mohd. Zubair Talha, “Realization of 2:4 reversible decoder and its applications” IEEE 2014 International Conference on Signal Processing and Integrated Networks (SPIN) .

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