Design, Optimization, and Modelling of Hybrid Organic-Inorganic Perovskite Memristors

CHAPTER 1: INTRODUCTION

The Fourth Basic Circuit Element

The three classic circuit elements we encounter in our basic circuit theory are resistors (𝑅), capacitors (𝐶) and inductors (𝐿). This figure shows the four basic circuit parameters and their relationship to basic circuit elements.

The First Memristor

When an external bias is applied, the boundary between two resistive regions moves, which changes the internal resistance of the device and thus the current through it [4]. D represents the total thickness of the switching layer and w(t) is a state variable representing the length. c) experimental RS I-V bipolar curve obtained from a Pt/TiO2−x/Pt memristor at HP Labs [4].

Types of Memristors

Filament-Type Memristor
Barrier-Type Memristor

In the case of a Schottky barrier type memristor, a Schottky barrier is formed at one of the metal|insulator interfaces and an ohmic contact at the other interface. Due to the redistribution of the atoms/vacancy/ions in the insulating layer, the barrier width and height change and consequently the resistance state of the device changes.

Figure 1.4: Schematic illustration of filamentary RS process in MIM structure. (a) Pristine device before electroforming

Memristor as Non-Volatile Memory

From the table it can be seen that the memristor has all the desired properties of the universal non-volatile memory [16]. The voltage on each bit line represents the input, which is multiplied by the conductance (data) of the corresponding cell stored locally according to Ohm's law.

Figure 1.6: (a) Digital type RS current-voltage characteristics useful for the application of memristors in ReRAMs [13]

Memristor as Artificial Synapse

This is the change in synaptic weight based on the relative timing between presynaptic and postsynaptic spikes. This is the change in synaptic weight based on the speed of the presynaptic spike and the postsynaptic spike.

Table 1.2: Terminology associated with neuromorphic computing

Motivation and Research Gaps

It is the sustained gain of synaptic weight through the application of repeated spikes at short intervals. It is the abrupt change in postsynaptic current due to the application of presynaptic spikes, which is also a measure of synaptic weight.

Formulation of the Problem Statement

Organization of the Thesis

The performance of devices fabricated on flexible substrates is also described in this chapter. In addition, based on the experimental data fitting and SPICE simulations, an algorithm is proposed to emulate memristive I-V characteristics.

In the work of Lehtonen et al., the state variable derivative has been modeled as a non-linear function of the voltage [71]. On the other hand, both 𝑉𝑆𝐸𝑇 and 𝑉𝑅𝐸𝑆𝐸𝑇 were observed to remain independent of the unit area.

CHAPTER 2: LITERATURE SURVEY

Materials for Memristors

Inorganic Materials
Organic Materials
Hybrid Organic-Inorganic Perovskites (HOIPs)

In addition to the above three-dimensional (3D) oxides, two-dimensional (2D) materials such as graphene, nitrides (e.g. BN), transition metal dichalcogenides (e.g. MoS2 and WS2), InSe, SnS, TiS2, etc., have also appeared up in this category [5-7]. 3D HOIPs (e.g., MAPbI3, FAPbI3, CsPbI3, etc.) are the earliest and have been most commonly used for memristors as well as for other optoelectronic devices [15,16].

Figure 2.1: (a) Schematic of the Pt/TiO 2-x /TiO 2 /Pt memristor structure and its representation in the form of two discrete resistances

Fabrication Methods of HOIP Memristors

In the report by Abdulla et al., the SPICE model considers tunneling through similar electrodes (with equal work function) giving rise to a rectangular tunneling barrier [82]. Such uncontrollable conductive paths in the film degrade the endurance and retention of the device.

Resistive Switching in HOIPs

Formation and Rupture of Conducting Filaments
Redistribution of Halide Ions and Vacancies or Ion Migration
Competition between CFs formed by Metal Ions and by Halide
Physicochemical Interaction at Perovskite|Electrode Interface
Hysteresis due to Electric Field-Driven Lattice Distortion

Applications and State-of-the-Art of HOIP Memristors

Data Storage
Artificial Synapse
Photonic and Logic Applications

Therefore, controlling the conductance by adjusting the shape of the synaptic plasticity is a goal of an artificial synapse [55]. The corresponding state diagram of the logic OR device, together with the gate symbol is shown in figure 2.6(c).

Figure 2.4: Mechanical flexibility of hybrid organic−inorganic perovskite RS memory devices, (a) I−V characteristics without and with bending stress, (b) bending stability with repetitive

Memristor Modelling

Dopant-Drift Model
Memristor–Rectifier Model
Tunnelling Barrier Model
SPICE Modelling

As shown in Figure 2.10, the model assumes that the memristor is a series connection of a resistor (Rs) with an electron tunneling barrier, and the width of the tunneling barrier is considered as the state variable. The TEAM model can be described in a SPICE micromodel, as shown in Figure 2.11(b), where the internal state variable is represented by the voltage across capacitor C and the bounds on the state variable are enforced by diodes D1 and D2.

Figure 2.7: Schematic representation of physical modelling approaches for RS memory. These models are broadly classified into three groups, based on scale, physical details and computational cost

Analytical Modelling of HOIP Memristors

By solving these differential equations numerically, the I-V characteristics of the MAPbI3 memristor can be accurately simulated (see figure 2.12(b)). Moreover, the model cannot adapt to the characteristics of devices with threshold switching behavior.

Summary

However, due to the deterministic nature of the model, it cannot address the stochastic characteristics of the HOIP memristor. However, they have high computational complexity and cost and do not address the stochastic nature of memristors.

With proper optimization of SR, 𝐼𝐶𝐶, frequency, etc. ON/OFF ratio and switching voltages can be significantly improved. Lehmann et al., "The phase diagram of a mixed halide (Br, I) hybrid perovskite obtained by synchrotron X-ray diffraction," RSC Advances, vol.

CHAPTER 3: UNDERSTANDING THE EFFECT OF MEASUREMENT

Chalcogenide Memristor

Device Structure and Working Principle
Manufacturer-Recommended Method

A photograph of the memristor IC and its internal arrangement is shown in Figure 3.1(a) and (b), respectively. As shown in Figure 3.2, 𝑉𝑆𝐸𝑇 increases as the frequency of the applied sinusoidal signal increases.

Figure 3.1: (a) Photograph of a Knowm 16 pin DIP package memristor IC. (b) Schematic of the internal arrangement of 8 memristors inside the DIP package

Alternative Electroforming Methods

Constant Voltage Bias
Linear Voltage Sweep
Linear Current Sweep
Pulse Voltage

Parts (a) and (b) show the currents in the respective devices, which have a value of 1 mA throughout, indicating that the devices are in LRS from the start of the sweep sweep. d) Switching cycles of the device formed with a constant bias of 0.2 V. Three switching cycles obtained from this device are shown in Figure 3.6(b), where the inset shows the applied triangular bipolar signal.

Figure 3.3: Switching cycles from devices formed using constant voltage bias of (a) 0.4 V, and (b) 0.3 V

Role of Characterization Parameters

Effect of Scan Rate Variation
Effect of Compliance Current Variation

𝐼𝐶𝐶 and the shutdown voltage (𝑉𝑆𝑇𝑂𝑃) during RESET are two operational parameters that change the HRS and LRS of the memristor. This is due to the migration of excess Ag+ ions into the active layer during the positive half of the switching cycle as a result of the large current flow.

Figure 3.8: (a) The forming step of two pristine memristors using two different SRs. (b) Switching cycles using three different SRs

Summary

Although the pulse shaping method is faster than the DC shaping methods presented here, the shaping time is longer than that of state-of-the-art memory devices. By properly optimizing the design time, it is possible to reduce the leakage current during operation and thus reduce energy consumption.

However, reducing the device thickness leads to a reduction in the ON/OFF ratio (see the red graph in Figure 6.8), which can affect the noise margin of the device. It was also found that the ON/OFF ratio increases with the thickness of the HOIP layer.

CHAPTER 4: MAPBI 3 BASED MEMRISTOR

Device Fabrication Process

In addition to the molar ratio of the solution, the stirring time and temperature were also varied for its optimization. Figure 4.1 (a) and (b) show the step-by-step fabrication process and a schematic of the HOIP memristive device, respectively.

Thin Film Characterization

Effect of Antisolvent

2D and 3D AFM images of films coated with and without antisolvent are shown in Figures 4.2 (a) and (b), respectively. A performance comparison of devices fabricated using these films is illustrated in the next section.

Electrical Characterization

Role of Scan Rate
Role of Compliance Current
Role of Device Area
Cycle-to-Cycle and Device-to-Device Variation

The corresponding variations of the switching parameters with 𝐼𝐶𝐶 are shown in Fig. 4.6(b), together with the device-to-device error calculated from 5 different devices for each value of 𝐼𝐶𝐶. Since the peak power consumption of the device depends on 𝐼𝑅𝐸𝑆𝐸𝑇, devices with a small area are desirable.

Figure 4.3: I-V characteristics of the memristive devices fabricated (a) with the use of toluene as the antisolvent and (b) without the use of antisolvent

Voltage Pulse Characterization

We have varied the amplitude (𝑉𝑅𝐸𝑆𝐸𝑇) and width (𝑡𝑅𝐸𝑆𝐸𝑇) of the RESET pulse for 10 initial cycles and determined their optimal values based on the obtained ON/OFF ratios. We have experimentally demonstrated this dilemma between the RESET pulse amplitude and width to optimize the ON/OFF ratio of the memristor.

Figure 4.9: (a) The schematic of one single cycle of the voltage pulse train that was used to carry out the endurance characterization, (b) 20 such cycles applied to the HOIP memristor (in red) and corresponding current switching (in blue), and (c) one o

Protocol for Memristor Characterization

Linearly Increasing Voltage Sweep Signal
Voltage Pulse Characterization

Therefore, a trade-off between these two parameters is necessary to achieve a certain ON/OFF ratio, i.e. a robust noise margin. As shown in Figure 4.10(c), we have obtained a consistent ON/OFF ratio close to 7 for at least 103 cycles.

Flexible HOIP Memristors

I-V Characteristics
Effect of Mechanical Stress

FESEM and AFM images of MAPbI3 films coated on glass and PET substrates are shown in Figure 4.12 and Figure 4.13, respectively. A FESEM image of a film coated on a rigid glass substrate clearly shows polycrystalline grains (see Fig. 4.12(a)).

Figure 4.11: (a) Schematic of the flexible memristor device. (b) XRD spectrum of the MAPbI 3

Summary

The resistive switching maintains an ON/OFF ratio of ∼100 for a hold voltage of >1000 cycles and both LRS and HRS were retained for 1350 seconds. However, the 𝑉𝐹𝑂𝑅𝑀𝐼𝑁𝐺 and ON/OFF ratio of these devices was found to deteriorate with increasing stress.

In this model, as shown in equations (5.1) and (5.2), the two different current conduction mechanisms in LRS and HRS are combined by a state variable 𝑥(𝑣, 𝑡). Mao et al., “Hybrid Dion–Jacobson 2D lead iodide perovskites,” Journal of the American Chemical Society, vol.

CHAPTER 5: MULTIFUNCTIONAL RS AND SPICE SIMULATION OF HOIP

Multifunctional Resistive Switching

Instances of multiple RS in the same cell were reported with different devices based on materials such as TiO2, BiFeO3, ZnS-Ag/CuAlO2, MoS2, CeO2, etc. However, most of them needed either memristive devices connected anti-serially (see figure ) 5.1(a)) or several active layers stacked between electrodes (see Figure 5.1(b)).

Multiple BRS in HOIP Memristors

Two Types of BRS in the Same Device
Effect of STOP Voltage
Endurance and Retention of the Two BRSs
CRS behaviour in HOIP Memristor

This may be due to the involvement of Joule heating in the RESET process in the case of Type B circuit [20]. The insets of Figure 5.3(a) and (b) show the respective changes in device current during the RESET process on the linear scale.

Figure 5.2: J-V characteristics of the devices corresponding to (a) Type A and (b) Type B switching

Resistive Switching Mechanism

Therefore, the RESET process in Type B circuit is dominated by Joule heating (see Figure 5.7(b)(ii)) rather than field-assisted migration of I ions, due to the lack of I ions in the BE to respond with. VI+s in the CF. The immutability of HRS with 𝑉𝑆𝑇𝑂𝑃, as shown in Figure 5.3(b), further supports the fact that field-driven migration plays little role in Type B switching.

Memristor Models

In contrast, during Type B switching (see Figure 5.7(b)(i)), a positive voltage at the BE attracts I− ions, which, instead of being accumulated, diffuse out through the BE [16]. The use of lower 𝐼𝐶𝐶 helps this process by forming a relatively weaker CF that can be broken by the heating effect of the applied field (7.89 kV/cm), which is lower than in the case of Type A switching [30 ].

Simulation of HOIP Memristor IV Characteristics

Modified Yakopcic Model Algorithm
Fitting Parameter Extraction for HOIP Memristor
SPICE Simulation of HOIP Memristor I-V Characteristics

The limit voltages 𝑉𝑝 and 𝑉𝑛 were extracted from the highest values of the rate of change of the current in the positive and negative voltage regime, respectively. Figures 5.12(a) and (b) show the results of fitting the experimental IV plots to the model equations for type A and type B switching with average errors per cycle of 6.93% and 7.28%, respectively.

Figure 5.8: The equivalent model circuit designed in SPICE; (a) the current source from which overall memristor current is achieved and (b) memristor subcircuit equivalent consisting of a

Summary

Although 3D HOIP memristors exhibit reliable RS behavior, it is difficult to control the shape, uniformity, and strength of the CFs. Analysis of the I-V characteristics showed that the current during HRS is dominated by the tunneling mechanism for A-type switching and by the diffusion current for B-type switching.

Xu et al., “Resistive switching memory for high-density storage and computing,” Chinese Physics B, vol. Pickett et al., "Switching Dynamics in Titanium Dioxide Memristive Devices," Journal of Applied Physics, vol.

Introduction

Lower-Dimensional HOIPs

Characterization of 2D BA 2 PbI 4 Memristors
Thickness Variation of BA 2 PbI 4 Layer

Memristors of the structure ITO|PEDOT:PSS|BA2PbI4|PCBM|Ag (schematically in Figure 6.4(a)) were fabricated according to the procedure described previously. Figure 6.7(a) and its inset show that 𝑉𝐹𝑂𝑅𝑀𝐼𝑁𝐺 increases with the thickness of BA2PbI4.

Figure 6.2: (a) Photograph of the spin-coated RP perovskite films for n=1 (yellow film), n=2 (red film), n=3 (blackish yellow film), and n=ꝏ (dark brown) and (b) the corresponding XRD spectra

Low-Temperature Performance of 2D HOIP Memristors

Temperature Dependence of LRS Current
Temperature Dependence of HRS Current

However, the method we used here is only an indirect method to investigate the components of CF. The 𝐸𝑎 value increases as deeper traps are activated at higher temperatures, and then, the HRS of the device decreases [7].

Figure 6.9: I-V plots BA 2 PbI 4 memristor taken at different temperatures, ranging from 200K to 300K

SPICE Simulation of 2D HOIP Memristors

Piecewise fitting of 2D memristor I-V characteristics shows that the LRS region fits a linear function indicative of ohmic conduction. These fitting parameters were then used in SPICE for the complete emulation of I-V curves of the 2D memristor.

Figure 6.12: (a) Calculation of threshold voltages (𝑉 𝑝 and 𝑉 𝑛 ) from the maximum slope points of the I-V characteristics

Summary

The 𝐸𝑎 value increases as the deeper traps are activated at higher temperatures and subsequently the device's 𝑅𝐻𝑅𝑆 decreases. SPICE simulation of the I-V characteristics of 2D HOIP memristors using the modified Yakopcic model gave an average error per cycle of 9.49%.

Byun et al., "Temperature-Driven Phase Transition of Organic-Inorganic Halide Perovskite Single Crystals," Journal of the Korean Physical Society, vol. In the future, such emerging applications of HOIP memristors can be explored using them in the form of a transverse array.

CHAPTER 7: CONCLUSION

Characterization of Chalcogenide Memristors

The devices formed using the positive voltage swing method have been found to give the most repeatable switching characteristics. Therefore, to get the optimum performance from the memristor, a trade-off must be made between power consumption and noise margin; therefore, selecting the right characterization parameters is essential for any new memristive device and such parameters have been identified.

Fabrication and Characterization of 3D HOIP Memristors

It has been found that a slower SR leads to relatively small formation and switching voltages, which help reduce power consumption during switching. On the other hand, a higher 𝐼𝐶𝐶 leads to a better ON/OFF ratio, but at the expense of higher 𝑉𝑅𝐸𝑆𝐸𝑇.

Model for SPICE Simulation of HOIP Memristor Characteristics .136

Limitations and Future Prospects

The next logical step in this research work is to implement the HOIP memristors in the form of crossbar architecture. This will increase storage density without major change in technology and will open up the use of these memristors for "in-memory computing".