The watermarking technique evolved from steganography. The use of watermarks is almost as old as the manufacture of paper. The operation of decoding is exactly opposite to that of encoding. The stego image is projected onto the 8-bit shift register. The same combinational circuit used in the decoding process.
HARDWARE REALISATION USING SPINTRONIC LOGIC
When the image needs to be retrieved, the secret code is retrieved using the same key. The watermark embedding technique converts the 2-D pixel values of the gray image and binary watermark into single integer (SI) data type and then converted to 1-D pixel values. Here, the 1-D stego image is first debuffered with the same private key and then these 1-d images are converted back to 2-d pixel values of the gray image and the binary code.
The above combination function is used for encoding the binary watermark into a gray image. Now, depending on the logical result of the combination function, either multiplexer results in binary bit to replace the third bit level position of the selected spatial pixel value or the pixel is left unchanged. Each of these circles represents a spin-polarized single electron confined in a quantum dot placed in a global magnetic field.
A weekly global magnetic field is applied externally, making the polarization at each point either parallel or antiparallel to the global field encoding the binary bit 1 and 0, respectively.
The charges circulating on the sphere represent small loops of electric current that create a magnetic field similar to the Earth's magnetic field. Immersing a spinning sphere in an external magnetic field changes its total energy according to how its spin vector is aligned with the field”[17]. In this work, we designed a spatial domain data embedding scheme and its hardware implementation using spin-based logic circuits with a two-dimensional array of spin-polarized electrons (cells).
24 | P a g e This logical operation is efficiently performed by the spin architecture depicted below in the figure. This unit is used to perform the watermark encoding operation by selecting the correct bit plane to generate the watermark signal prescribed for realizing the system. This device imports the spatial pixel values into the subsequent encoder/decoder circuits as well as exports or loads the output watermarked signal pixels or decoded data.
Spintronics technology, unlike conventional electronics technology, uses an electron 'spin' in addition to its charge to transfer and store information. Magnetic tunnel junctions (MTJs) are spintronic devices that exhibit two different resistance states due to tunneling magnetoresistance (TMR). effect.
INTRODUCTION TO SPIN-TRONIC LOGIC
We use a new 'combination by neutralization' design technology to combine individual component designs into multi-functional units. A spintronics-based ALU has the potential to offer significant area, time, and power advantages over conventional CMOS-based ALUs. The design of ALUs using individual MTJs uses a new design technique known as merge with neutralization, which combines these individual functions of addition, subtraction, and logic operations to produce an ALU.
Operation of field driven magnetic tunnel junction
31 | P a g e respectively with a parallel and antiparallel relative magnetization direction of the free layer with respect to the fixed layer. Magneto resistance ratio (MR) is defined as the ratio of differential resistance to ground resistance, i.e., RH and RL can be used to represent the binary states of logic0 and logic1 respectively in digital logic.
These states are non-volatile because they are ferromagnetic in nature and the free layer does not lose its magnetization even when the magnetic field used to polarize it is removed. 32 | P a g e Two current-carrying planes are placed above the free layer such that when current flows through them, they generate a magnetic field that polarizes the free layer in a direction parallel or anti-parallel to the pinned layer. When both currents are in the same direction, a net magnetic field is produced. When the extra plane z carries enough current, under an existing magnetic field due to current in input planes A and B, the pinned layer is magnetized in the same direction as the free layer.
33 | If the pinned layer were in the opposite direction, the output would be exactly the complement 'R'.
Spin Torque Transfer
In this case, sense amplifiers are used. Typically, one or more MTJs are connected in series to the positive and negative terminals of the sense amplifier as shown in the figure below. According to the corresponding inputs, all states of the MTJ resistor are in logic step. In the case of generating an output, a small sense current is applied to the MTJ, resulting in the generation of a small voltage, the magnitude of which is entirely based on the combined resistance of the MTJ connected to the terminal. 35 | Page Now comes the role of the sense amplifier, which then amplifies the voltage difference between the +ve and –ve terminals and outputs a voltage of 0V if the resistors are equal in size, otherwise outputs a voltage of 5V if the resistors are not the same.
Design of ALU components
There is another sense amplifier that produces the output of logic function [(R1+R2)-(R4+R5). This function indicates Bolt. The design of 1-bit logic units that perform the logic function of AND , OR , NAND , NOR , XOR and XNOR is depicted in the following figure. In the TMR-based circuits, since output depends on the state of each device connected in series, it is not always possible to combine two circuits directly.
In cases where it is possible, there are some challenges produced by the logic of sensitivity. In practice, this type of design presents certain difficulties and must implement several control inputs to ensure that addition is performed for a certain number of control inputs and subtraction for others.
Concept of union with neutralization
So the design works in exactly (2n+1) times units. The modified design uses "union with neutralization" to combine logic functions into a single unit. In general, 2 separate MTJ based units, when combined directly, give a completely different truth story from the desired truth table or one of their truth table. When AND gate and NAND gate are combined they generate the output something like this. When MTJs have more than one input, it cannot be easily neutralized using a control input. Additional MTJs are used to perform the same function as MTJs connected to the opposite terminal of the sense amplifier. Then this state can be transferred by using the spin-torque transfer technique. to MTJs, neutralizing MTJs on both sides. Eg: To construct a logic unit that performs the operations of AND, OR, NAND and NOR, neutralization using control inputs and using logic can be used.
45 | P a g e Logic device that performs AND ,OR ,NAND and NOR using neutralization at control input through logic. Second step: MTJ R2 is neutralized by transferring the state of R6 to it. For this purpose, control input X4 is high. The table shows the logic values of control inputs required for each function of the ALU.
When the three control steps are extended to n-bit, the last step overlaps with the first step of the next unit.
Construction of RS flip-flop using logic gates
The most basic flip-flop is the RS flip-flop, and it has two inputs, labeled set(S) and reset(R). 53 | P a g e When the value of Ctrl is set to logic 0, the MTJ combination combines as a NAND gate to form an RS flip-flop. The manufacture of MTJ technology is still carried out in laboratories. Intensive studies are carried out to improve the properties of the device. In the field of digital electronics, spintronic logic is like an infant, and only the qualitative comparison is possible with the mature CMOS technology. A 1-bit ALU that performs the 8 functions is constructed using CMOS technology, requiring almost 50 45nm transistors, which entirely depends on the requirements and the design. Currently, an MTJ can be fabricated as short as 40nm in laboratories. However, the actual dimension of can vary and depend on number of factors such as desired TMR, thickness of barrier layer, material selection, magnetic hardness of the layer, etc.
The propagation in the CMOS ALU is about 5 logic gates. Rather, the delay of the MTJ ALU is 3 control steps where each step has 1-MTJ device delay of the order of nanoseconds. Unlike CMOS technology, MTJs are low power devices. So 20 MTJ ALU is power efficient. The main disadvantage of MTJ ALU design is that it uses more control signals than a CMOS-based ALU. The digital watermarking technique is analyzed using conventional FPGA and spintronics. The comparison was made based on analysis of results. Logic gates and flip-flops using spintronic devices are characterized by non-volatility, noise immunity, robustness, programmability and low power requirements. The devices and systems built with the help of MTJ are expected to have these advantages over those built is with the help of conventional silicon-based transistors.
We made an effort to analyze the new field of spintronics to explore its potential in the digital electronics world. We have analyzed and presented the design of 1-bit arithmetic and logic unit and RS flip-flop using MTJ elements and sense amplifiers and enumerated the control signals required for its operation. We have established a formal method in the design development for a bottom-up design with TMR devices. ,while this analytical work is a chancellor to introduce and elaborate this new technology while characterizing a design challenge and proposing a solution.
