Implementation of Convolutional Codes for Space Link Protocol

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ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE)

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ISSN (PRINT) : 2320 – 8945, Volume -3, Issue -3, 2015 14

Implementation of Convolutional Codes for Space Link Protocol

1Kumar Ragavendra.P, ²Nithin.A, ³Sriram.G.Bhagwat, ⁴Varsha.M, ⁵S.M.Vijaya

1,2,3Dept of ECE, RRCE, Bengaluru

Email: ¹[email protected], ²[email protected], ³[email protected],

4[email protected], ⁵[email protected]

Abstract: Convolutional codes are non-blocking codes that can be designed to either error detecting or correcting. Convolution coding has been used in communication systems including deep space communication and wireless communication. At the receiver end the original message sequence is obtained from the received data using Viterbi decoder. It implements Viterbi Algorithm which is a maximum likelihood algorithm, based on the minimum cumulative hamming distance it decides the optimal trellis path that is most likely followed at the encoder. In this paper we present the convolution encoder and Viterbi decoder for constraint length 7 and bit rate 1/2.

Keywords - Convolution Encoder, trellis diagram, Verilog HDL, Viterbi algorithm, Viterbi decoder.

I. INTRODUCTION

Convolutional codes represent one technique within the general class of channel codes. Channel codes (also called error correction codes) permit reliable communication of an information sequence over a channel that adds noise, introduces bit errors, or otherwise distorts the transmitted signal. Elias introduced convolutional codes in 1955. These codes have found many applications, including deep-space communications and voice band modems. Convolutional codes continue to play a role in low- latency applications such as speech transmission. Lattice’s Convolutional Encoder core is a parameterizable core for convolutional encoding of a continuous input data stream.

The core allows variable code rates, constraint lengths and generator polynomials. The core also supports puncturing. Puncturing enables a large range of transmission rates and reduces the bandwidth requirement on the channel. In this Paper we will concentrate on rate-1/n binary linear time- invariant convolutional codes, which are the simplest to understand.

II. CONVOLUTION ENCODER

Encoding of convolutional codes can be accomplished using simple registers. In convolutional encoder, the message stream continuously runs through the encoder unlike in the block coding schemes where the message is first divided into long blocks and then encoded.

Thus the convolutional encoder requires very little buffering and storage hardware. In this convolutional encoder, the following notations are used.

The basic requirements of a Convolutional system for space protocol are:

(1) Nomenclature: convolutional code with maximum- likelihood decoding.

(2) Code rate (r): 1/2.

(3) Constraint length (K): 7 bits.

(4) Connection vectors: G1 = 1111001 (171 octal); G2 = 1011011 (133 octal).

Fig.1. Convolutional encoder

One reason why this is important is that in digital modulation communications systems (such as wireless communication systems, etc.) noise and other external factors can alter bit sequences. The purpose of a convolutional encoder is to take a single or multi-bit input and generate a matrix of encoded outputs.

III. VITERBI DECODER

The viterbi algorithm is used to decode convolutional codes and any structure or system that can be described by a trellis. It is a maximum likelihood decoding algorithm that selects the most probable path that maximizes the likelihood function.

The algorithm is based on add-compare-select the best path each time at each state.

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Fig. 2 Block diagram of Viterbi decoder Fig.2 shows the block diagram of viterbi decoder. It consists of the following modules:

Branch Metric Unit, ACS, State Metric Storage, Survivor Path Metric, Traceback and Output Decode Block.

BRANCH METRIC UNIT

At the decoder side, we receive analog signal. Analog signal is a mixture of transmitted signal and noise signal.

The branch metrics measure the difference the received symbol and the symbol that causes the transitions between states in the trellis. The branch Metric Unit consists of EXOR Gate and 3-bit counter.

Fig. 3 Branch Metric Calculation

BMU compares the received data signal with the expected data code and it will count the number of the differing bits through 3-bit counter. The 3-bit counter is designed by cascading the DFF output of one flip flop is given as the clock input to the other flip flop.

Add Compare Select Unit (ACS)

The Add compare and select Unit adds the output of the branch Metric to the corresponding path metrics the added result that is new path metric is stored in the Path Metric Memory. An ACS unit receives output of two Branch Metric Unit and two path metrics.

The two adders compute the partial path metric of each branch, the comparator compares the two partial metrics, and the selector selects an appropriate branch.

The new partial path metric updates the state metric of state p, and the survivor path- recording block records the survivor path. The number of necessary ACS module is equal to half the number of total states.

PATH METRIC CALCULATION AND STORAGE The Path Metrics are updated in two steps. First for each of the two incoming paths, the corresponding Branch Metric is added to the Path Metric of the original state.

The two sums are compared and the larger one is stored as the new Path Metric and the corresponding path is stored as the best path.

3.5 TRACEBACK UNIT

Traceback begins after completing the metric update of the last symbol in the frame. For frame by frame Viterbi decoding, all that is needed by the traceback algorithm are the state transitions. The starting state is state 00. For sliding window decoding, the starting state is the state with the largest state metric.

Two basic operations are performed in the traceback SMU (Survivor Memory Unit).These operations are explained below:

Writing New Data (WR): Survivor vector is generated by the ACS unit it needs to be written into the memory.

Each individual survivor is written into a memory position that corresponds to its state. The write pointer moves forward (from the left to the right in Figure 6) through the memory as the ACS unit moves on to each new stage in the code trellis.

Decode Read (DR): Once D (or more) survivor vectors have been written to memory, the SMU needs to start tracing a path back to the origin of the trellis in order to decode the output bits.

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Functionally decode read operation is identical to the trace back read operation, except that the pointers read from memory are decoded to form the output of the SMU.

Here, we omit the traceback read operation because we know the starting point (state 0) of the traceback operation. We decode data directly. Decode read starting point is the end of the frame (state 0). This state has a decision bit either 0 or 1 in SMU. This decision bit is now extracted and is stored into FILO buffer.

Depending on the decision bit we can find previous state and its decision bit. Process is continuing till the starting point of the frame.

Decode read operation frees up memory space for use by the write operation. Since the memory size in hardware is limited, the write operation must fill the space freed up by decode read operation.

IV. FPGA IMPLEMENTATION RESULTS

Verilog is used for coding the designs and FPGA flow is taken for implementation. The design is targeted to Spartan 3 FPGA using Xilink ISE foundation series.

V. CONCLUSION

Viterbi decoder is one of the most important blocks in space data communications. In this paper we have designed and implemented the Viterbi decoder targeting FPGA implementation. Our aim is to design an efficient decoder with an error correcting capability upto 2-bits.

Also the design can be extended to higher input data rates.

REFERENCES

[1] www.ccsds.org Recommendation for Space Data System Standards, BLUE BOOK,TM synchronization and channel coding

recommended standard CCSDS 131.0-B- 2,August 2011.

[2] J. A. Heller and I. M. Jacobs, Viterbi Decoding for Satellite and Space Communications," IEEE Transactions on Communication Technology, vol. COM-19, October, 1971, pp. 835-848.

[3] P. Elias, Coding for noisy channels, Proc. IRE Conv. Rec.part 4• 37–46 (1955) (this paper is also available in Ref. 2). Q2.

[4] E. R. Berlekamp, ed., Key Papers in the Development of Coding Theory, IEEE Press, 1974.

[5] S. Lin and D. J. Costello, Jr., Error Control Coding: Fundamentals and Applications, Prentice-Hall, 1983.

[6] Wei Chen, “RTL Implementation of Viterbi Decoder,” Master’s thesis, Linkoping Uni. Rep, pp.6- 25, 2006.

[7] Samirkumar Ranpura and Dong Sam Ha, “Low- Power Viterbi Decoder Design for Wireless Communications Applications,” Int. ASIC conference, Sept. 1999, Washington, D.C.

[8] B. Sklar, Digital Communications: Fundamentals And Applications, Prentice-Hall, 2nd Edition, 2002.

[9] G.Feygin and P.G.Gulak, “Survivor Sequence memory management in viterbi decoders,” CSRI Tech.Rep.262, Univ.of Toronto, Jan1991.

[10] Z. M. Patel, “VLSI implementation of IEEE802.11a Physical layer baseband”, M.Tech Dissertation, IITB, Powai. 2009.

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