Inaugural of IEEE Student Branch of - BVM Engineering College

A Report on

Inaugural of IEEE Student Branch of

Birla Vishvakarma Mahavidyalaya Engineering College, Vallabh Vidyanagar

&

IEEE Organized Two days Workshop on VLSI system design and Verification using Verilog and system Verilog programming

Languages

Date: 29

^th

August 2016 to 30

^th

August 2016

Organized by

Electronics & Communication Engineering Department BVM Engineering College (An Autonomous Institution)

(Managed by Charutar Vidya Mandal)

Vallabh Vidyanagar-388120

Inaugural of IEEE Student Branch of

Birla Vishvakarma Mahavidyalaya Engineering College

The Inaugural Function of IEEE student branch of Birla Vishvakarma Mahavidyalaya Engineering College was held on 29^th August, 2016 at 10:00 am onwards. The IEEE student branch was inaugurated by Dr. I. N. Patel, Principal, BVM College & president of the function, Dr. P. M. Udani, Director, ISTAR & Chief guest of the function, Prof. Rakesh Patel, Assistant Professor and IEEE Region-10 SAC Project Co-Ordinator, Dr. Mehul B. Shah, Head, EC department, Prof. Darshan C. Dalwadi (IEEE branch Counselor of BVM) and other faculty members of BVM Engineering College.

Dr. I. N. Patel, Principal, BVM gave his valuable presidential remarks by encouraging the participants to avail utmost benefit from the workshop and explore themselves in the respective research areas. He congratulates to the faculty members for getting IEEE student branch at BVM Engineering College. He thanked CVM for its continuous motivation and help extended to conduct such programs.

Dr. P. M. Udani, Director, ISTAR and Ex-Scientist ISRO, explained the importance of IEEE. He also encouraged the students and faculty members towards the benefit of IEEE membership. He thanked BVM for invite us on the occasion of inaugural function of IEEE student branch.

Prof. Darshan C. Dalwadi, IEEE branch Counselor of Birla Vishvakarma Mahavidyalaya Engineering College gives the complete information about IEEE student branch activity. He also motivate the students towards IEEE membership and provide the guidance towards how to take the IEEE membership.

He thanked, Dr. I. N. Patel sir for providing support regarding selection of IEEE student branch at BVM Engineering College. He also thanked Dr. Mehul B. Shah for providing guidance in IEEE student branch. He also thanked all the faculty members and student chair Dhruvaj Suryavanshi and all other IEEE student members for getting IEEE student branch at BVM Engineering College.

Prof. Rakesh Patel, IEEE Region-10 SAC Project Co-Ordinator, gives the information on IEEE student membership. He also motivates and encourages the students towards the IEEE membership. He also explains the benefits of IEEE membership. He also gives the region wise information of IEEE members and various activities under IEEE.

IEEE Organized Two days Workshop on VLSI system design and Verification using Verilog and system Verilog programming

Languages

IEEE student branch of Birla Vishvakarma Mahavidyalaya Engineering College organized two days workshop on “VLSI system design and Verification using Verilog and system Verilog programming languages” on 29^th August and 30^th August 2016. This workshop is organized by Electronics and Communication department with the association of Einfochips limited, Ahmedabad. Dr. Mehul B. Shah, Prof. Darshan C. Dalwadi and Prof. Amit H. Choksi are the coordinator of the workshop. There are total 40 participants are registered in this workshop. There are 3 experts which are coming from Einfochip Limited, Ahmedabad.

Students Participants in the Workshop

On first day, the expert Mr. Kamlesh explained the Verilog programming languages and its application in industry.

Date: 29/8/2016 Mr. Kamlesh from Einfochip explained HDL languages On first day, the expert Mr. Siddhesh demonstrated the hardware to the students.

Date: 29/8/2016 Mr. Siddhesh from Einfochip demonstrated the hardware

On second day, the expert Mr. Ankit Sheth explained the verification and System Verilog programming language to the students.

Date: 30/8/2016 Mr. Ankit Sheth from Einfochip explained the verification and System Verilog programming language