Hall Ticket No Question Paper Code: AEC002
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
Dundigal, Hyderabad - 500 043IV B.Tech III Semester End Examinations, November - 2018
Regulation: IARE-R16
DIGITAL SYSTEM DESIGN
(Electronics and Communication Engineering)
Time: 3 Hours Max Marks: 70
Answer any ONE question from each Unit All questions carry equal marks
All parts of the question must be answered in one place only
UNIT – I
1 a) Given the 4-bit data word 1100, generate the 7-bit composite word for the hamming code that corrects and detects single errors.
[7M]
b) Perform the following Subtraction using 2’s complement.
i) 15-17 ii) 25-13
[7M]
2 a) Convert the following octal numbers to their Decimal equivalent numbers.
i) 705.56 ii) 645
[7M]
b) Perform the following addition using excess-3 code.
i) 386+756 ii) 1010 + 454
[7M]
UNIT – II 3 a) State and prove the following Boolean laws.
i) Associative law ii) Distributive law iii) De-Morgan’s law
[7M]
b) Convert the following Boolean expression into standard SOP form (i) f(A,B,C)= AC’+A’B’C’+A’B’
(ii) (ii) f(A,B,C)= AB+B’C’+A’C
[7M]
4 a) Design BCD to Gray code converter and realize using logic gates? [7M]
b) Using the tabular method, obtain the minimal expression for f = ∑m (2,6,8,9,10,11,14,15) [7M]
UNIT – III
5 a) Design a combinational circuit with three inputs and one output. The output is 1 when the binary value of the inputs is less than 3, otherwise the output is zero.
[7M]
b) Design 3 bit gray code to binary code converter using logic gates. [7M]
MODEL QUESTION PAPER
6 a) Design and implement a 4 bit binary parallel adder. [7M]
b) Implement full subtractor using half subtractor. [7M]
UNIT – IV
7 a) Explain the operation of SR flip-flop with the help of circuit diagram
.
[7M]b) Draw the logic diagram of a SR latch using NOR gates. Explain its Operation using excitation table.
[7M]
8 a) Design synchronous mod 4 up counter using JK flip-flops. [7M]
b) Design D flip-flop into T and JK flip-flops. [7M]
UNIT – V
9 a) List out capabilities and limitations of finite state machines. [7M]
b) Draw the merger graph and obtain the set of maximal compatibles for the incompletely specified machine whose state table is given below.
PS NS,Z
X=0 X=1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
[7M]
10 a) Distinguish between mealy and moore machine, and draw the state diagram for the following Mealy machine.
PS NS,Z
X=0 X=1
A C,0 B,0
B A,1 D,0
C B,1 A,1
D D,1 C,0
[7M]
b) A clocked sequential circuit is provided with a single input x and single output z, whenever the input produces a string pulsed 111 or 000 and at the end of the sequence it produces an output z=1 and overlapping is also allowed.
i) Obtain state diagram and state table.
ii) Find equivalence classes using partition method.
[7M]
INSTITUTE OF AERONAUTICAL ENGINEERING
(Autonomous)
Dundigal, Hyderabad - 500 043I. COURSE OBJECTIVE
The course should enable the students to:
S.No Description
I Formulate and solve problems involving number systems and operations related to them and generate different digital codes.
II Describe and analyze functions of logic gates and optimize the logic functions using K - map and Quine - McClusky methods
III Demonstrate knowledge of combinational and sequential logic circuits elements like Adders, Multipliers, flip-flops and use them in the design of latches, counters, sequence detectors, and similar circuits.
IV Design a simple finite state machine from a specification and be able to implement this in gates and edge triggered flip-flops.
II. COURSE LEARNING OUTCOMES
Students who complete the course will have demonstrated the ability to do the following.
CAEC002.01 Understand number systems, binary addition and subtraction, 2’s complement representation and operations with this representation and understand the different binary codes.
CAEC002.02 Illustrate the switching algebra theorems and apply them for reduction of Boolean function.
CAEC002.03 Identify the importance of SOP and POS canonical forms in the minimization or other optimization of Boolean formulas in general and digital circuits.
CAEC002.04 Discuss about digital logic gates and their properties, and implement logic gates using universal gates.
CAEC002.05 Evaluate functions using various types of minimizing algorithms like Boolean algebra.
CAEC002.06 Evaluate functions using various types of minimizing algorithms like Karnaugh map or tabulation method
CAEC002.07 Design Gate level minimization using K-Maps and realize the Boolean function using logic gates.
CAEC002.08 Analyze the design procedures of Combinational logic circuits like adder, binary adder, carry look ahead adder.
CAEC002.09 Understand bi-stable elements like latches, flip-flop and illustrate the excitation tables of different flip flops.
CAEC002.10 Analyze and apply the design procedures of small sequential circuits to build the gated latches.
CAEC002.11 Understand the concept of Shift Registers and implement the bidirectional and universal shift registers.
CAEC002.12 Implement the synchronous counters using design procedure of sequential circuit and excitation tables of flip – flops.
CAEC002.13 Implement the Asynchronous counters using design procedure of sequential circuit and excitation tables of flip – flops.
CAEC002.14 Understand and analyze the design of a finite state machine and implement Moore and mealy machine.
CAEC002.15 Understand and analyze the merger chart methods like merger graphs, merger table for completely and incompletely specified machines.
CAEC002.16 Apply the concept of digital logic circuits to understand and analyze real time applications.
CAEC002.17 Acquire the knowledge and develop capability to succeed national and international level competitive examinations.
III. MAPPING OF SEMESTER END EXAMINATION TO COURSE LEARNING OUTCOMES:
SEE
Question No. Course Learning Outcomes
Blooms Taxonomy
Level
1
a CAEC002.01 Understand number systems, binary addition and subtraction, 2’s complement representation and operations with this representation and understand the different binary codes.
Understand
b CAEC002.01 Understand number systems, binary addition and subtraction, 2’s complement representation and operations with this representation and understand the different binary codes.
Understand
2
a CAEC002.01 Understand number systems, binary addition and subtraction, 2’s complement representation and operations with this representation and understand the different binary codes.
Understand
b CAEC002.01 Understand number systems, binary addition and subtraction, 2’s complement representation and operations with this representation and understand the different binary codes.
Understand
3
a CAEC002.02 Illustrate the switching algebra theorems and apply them for reduction of Boolean function.
Remember b CAEC002.03 Identify the importance of SOP and POS canonical forms in the
minimization or other optimization of Boolean formulas in general and digital circuits.
Remember
4
a CAEC002.06 Evaluate functions using various types of minimizing algorithms like Karnaugh map or tabulation method
Understand b CAEC002.06 Evaluate functions using various types of minimizing algorithms
like Karnaugh map or tabulation method
Understand
5
a CAEC002.08 Analyze the design procedures of Combinational logic circuits like adder, binary adder, carry look ahead adder.
Understand b CAEC002.08 Analyze the design procedures of Combinational logic circuits
like adder, binary adder, carry look ahead adder.
Understand
6
a CAEC002.08 .
Analyze the design procedures of Combinational logic circuits like adder, binary adder, carry look ahead adder.
Understand b CAEC002.08 Analyze the design procedures of Combinational logic circuits
like adder, binary adder, carry look ahead adder.
Understand
7
a CAEC002.10 Analyze and apply the design procedures of small sequential circuits to build the gated latches.
Understand b CAEC002.09 Understand bi-stable elements like latches, flip-flop and illustrate
the excitation tables of different flip flops.
Remember
8
a CAEC002.09 Understand bi-stable elements like latches, flip-flop and illustrate the excitation tables of different flip flops.
Remember b CAEC002.12 Implement the synchronous counters using design procedure of
sequential circuit and excitation tables of flip – flops.
Understand
9
a CAEC002.14 Understand and analyze the design of a finite state machine and implement Moore and mealy machine.
Understand b CAEC002.15 Understand and analyze the merger chart methods like merger
graphs, merger table for completely and incompletely specified machines.
Understand
10
a CAEC002.14 Understand and analyze the design of a finite state machine and implement Moore and mealy machine.
Understand b CAEC002.15 Understand and analyze the merger chart methods like merger
graphs, merger table for completely and incompletely specified machines.
Understand
