Low Latency Architecture of Novel Decimal Matrix Code Algorithm

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International Journal of Recent Advances in Engineering & Technology (IJRAET)

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ISSN (Online): 2347 - 2812, Volume-5, Issue -6, 2017 41

Low Latency Architecture of Novel Decimal Matrix Code Algorithm

1K.Ramesh Babu,²C. Jaya Kumar,³Suman Sekhar,⁴N.Umapathi, ⁵K. DurgaAparna, ⁶V.Gajendra Kumar

1,2,3Professor, Dept. of E.C.E., P.I.T.S., Ongole&^4,5,6Assoc. Professor, Dept. of E.C.E., P.I.T.S., Ongole,

Abstract: Transient multiple cell upsets (MCUs) causes major issues with regard to the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. So novelty is being imposed by matrix codes (MCs) based on hamming codes have been proposed for memory protection.

The proposed DMC utilizes decimal algorithm toobtain the maximum error detection capability. Moreover,the encoder-reuse technique (ERT) is proposed to minimizethe area overhead of extra circuits without disturbing thewhole encoding and decoding processes. ERT uses DMCencoder itself to be part of the decoder. Further, this project is enhanced using square root carry select adder for improving propagation delay.

I. INTRODUCTION

The general idea for achieving error detection and correctionis to add some redundant bits (i.e., some extra data) to a message, which receiver can use to check consistency of thedelivered message, and to pick up data determined to be corrupt. Error-detection and correction scheme can be eithersystematic or non-systematic: In a systematic scheme, the transmitter sends the unique data, and attaches a fixednumber of redundant bits, based on particular logic. If onlythe error detection is required, a receiver can check the samelogic to the received data bits and compare its output with thereceive check bits; if the values do not match, an error hasoccurred at some point throughout the transmission.

Differenttypes of codes used for Error detection and correction. In a system to uses a non-systematic code, the message istransformed into an encoded message that has at least asmany bits as that message.

II. LITERATURE SURVEY

The general platform for error correction code is different from the error correction in speaking and writing [1].

Single-bit error correction (SEC) codes can be maximized in mitigating MCU errors when used together with the interleaving structure in memory designs. The model proposed in this paper provides failure probability to probabilistically demonstrate the benefits of various interleaving scheme selections for the memories with SEC. Grouped events such as MCU are

taken into account in the proposed model by using the compound Poisson process. As a result of the proposed model, designers can perform predictive analysis of their design choices of interleaving schemes [2].

During memory process the other type of faults can occur which is called Single Event Upset (SEU) [3].

A Matrix code, combines Hamming and Parity codes to assure the improvement of reliability and yield of the memory chips in the presence of high defects and multiple bit-upsets. The method is evaluated using fault injection experiments [4].

Multiple Bits Upsets (MBUs) are becoming an increasingly important factor in the reliability of memories exposed to radiation effects. To address this issue, Built-in Current Sensors (BICS) have recently been applied in conjunction with Single Error Correction/Double Error Detection (SECDED) codes to protect memories from MBUs [5].

MBUs are presented in memories, the errors induced by several events may overlap each other, which is more frequent than single event upset (SEU) case.

Furthermore, radiation experiments show that the probability ofMBUs strongly depends on angles of the radiation event [6].

In [7] two fault tolerance techniques, Hamming code and Triple Modular Redundancy (TMR),that are largely used to mitigate Single Event Upsets in integrated circuits, in terms of area and performance penalty. Both techniques were implemented in VHDL and tested in two target applications: arithmetic circuits with pipeline and registers files. Area overhead results show that TMR is more appropriated for modules using single registers like in pipelines, control and datapath circuits, while Hamming code is a better trade-off for groups of registers, such as register files, caches and embedded memories.

Single error correction codes (SEC), are common techniques to protect memories against multiple cell upsets (MCUs). This kind of errors is increasingly important as technology scales, becoming a prominent effect, and therefore greatly affecting the reliability of memories. Ideally, the interleaving distance (ID) should be chosen as the maximum expected MCU size. In this way, all errors in an MCU would occur in different

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logical words, thus being correctable by the SEC codes [8].

In [9] concatenated Reed-Solomon code with a Hamming code for dynamic random access memory (DRAM) controller. The concatenated code consists of a Reed-Solomon outer code, two shortened Reed- Solomon codes, and a Hamming inner code. The proposed code takes the advantages of Reed-Solomon codes and Hamming codes to protect DRAM memory data against single event upsets and multiple bit upsets.

III. PROPOSED SYSTEM

The contribution of this paper is a novel decimal matrix code (DMC) based on divide-symbol is implemented to provide enhanced memory reliability. The implemented DMC utilized decimal algorithm (decimal integer addition and decimal integer subtraction) to identify errors. By usingdecimal algorithm is that the error detection capability was maximized so that the reliability of memory was enhanced.

Besides, the encoder-reuse technique(ERT) was implemented to minimize the area overhead of extra circuits (encoder and decoder) without disturbing the whole encoding and decoding processes, because ERT use DMC encoder itself to be part of the decoder.

In the proposed scheme, the circuit area of DMC is minimized by reusing its encoder. This is called the ERT.The ERT can reduce the area overhead of DMC withoutdisturbing the whole encoding and decoding processes. Itcan be observed that the DMC encoder is also reused forobtaining the syndrome bits in DMC decoder. Therefore, thewhole circuit area of DMC can be minimized as a result ofusing the existent circuits of encoder. Besides, this figure alsoshows the proposed decoder with an enable signal fordeciding whether the encoder needs tobe a part of thedecoder. In other words, the En signal is used fordistinguishing the encoder from the decoder, and it is underthe control of the write and read signals in memory.

Therefore, in the encoding (write) process, the DMC encoderis only an encoder to execute the encoding operations.

However, in the decoding (read) process, this encoder isemployed for computing the syndrome bits in the decoder.

These clearly show how the area overhead of extra circuitscan be substantially reduced. In the proposed

DMC, first, thedivide-symbol and arrange-matrix ideas are performed.

The N-bit word is divided into k symbols of m bits (N = k ×m), and these symbols are arranged in a k1× k2 2-D matrix (k= k1× k2, where the values of k1 and k2 represent the numbersof rows and columns in the logical matrix respectively).

Second, the horizontal redundant bits H are produced byperforming decimal integer addition of selected symbols perrow. Here, each symbol is regarded as a decimal integer.

Figure 1 Fault tolerance memory with DMC.

Figure 2.

32 Bit word which can be divided into 8 symbols.

Figure 3.

Delay and area evaluation.

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Figure 4.

Carry select Adder.

IV. RESULT

Figure 5.

Figure 6.

Figure 7. Improved performance of DMC.

V. CONCLUSION

In this research project, novel per-word DMC wasproposed to assure the reliability of memory. The protectioncode utilized decimal algorithm to detect errors, so that moreerrors were detected and corrected.

The obtained resultsshowed that the implemented scheme has a superiorprotection level against large MCUs in memory. Besides, theimplemented decimal error detection technique is anattractive opinion to detect MCUs in CAM because it can becombined with CSA to provide an adequate level ofimmunity.

REFERENCES

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