The main goal of this work is to develop a quantum transport model for graphene-based field effect transistors. Various forms of graphene-based field-effect transistors are being investigated to determine their suitability for digital and/or analog/RF applications.
Motivation
Although these architectures currently help, achieving physical dimensions close to the 'deep nanometer' regime above 20 nm is a challenge for existing technologies [8]. Chipmakers have moved from 20-nm to 14-nm, but Continuous performance improvements are phasing out [9] due to: 1) no economic advantage, 2) requiring additional circuitry to track and accommodate performance variations, and 3) density improvement is closer to 1 .6 × and not 2 ×. The International Technology Roadmap for Semiconductors (ITRS) refers to future transistor scenarios as 'More-Moore', 'More-than-Moore' and 'Beyond-CMOS' [10].
Graphene for Electronics
Some of the target applications of graphene include digital electronics [13], radio frequency (RF) electronics, [14], advanced sensors [15], semi-transparent electronics [16], low power switches [17], solar cells [18], and battery -energy storage [19]. While most of the research works with graphene have focused on replacing the silicon channel, some groups have come up with various ideas to induce an energy gap in graphene, such as the formation of nanoribbon [23], bilayer graphene [24], chemical modified graphene [25] and single electron transistor [26].
Transistor Figure of Merits and Trade-off
The important performance metric for RF transistors is the unity current gain frequency or cutoff frequency (fT), which represents the maximum operating frequency at which a transistor can prove useful. Another important parameter of RF transistor is the maximum oscillation frequency or unity power gain frequency (fmax).
State-of-art of Graphene-based MOSFETs
Digital Electronics Applications
The experimental studies on BLG FETs have reported an energy gap of 200-250 meV and a maximum ON/OFF current ratio of about 100, which is significantly smaller for the switching requirement [28, 44], as shown in Table 1.1. So far, BLGNR FETs have a small ON/OFF current ratio for the switching needs, but they have shown a significant energy gap at a very narrow width.
Analog Electronics Applications
In summary, graphene is well suited for use in high-performance TFET due to ultra-body thickness, but many challenges exist for the experimental realization of graphene-based TFET. GNR FETs are not very popular for RF applications due to low ON current which can degrade the cutoff frequency.
Modeling of Nanoscale Devices
In the steady state, the governing equations for the delayed (Gr), smallest (G<), and largest (G>) Green's functions can be written [94] as. On the other hand, in the consideration of diffusive transport, the carrier distribution is treated by introducing Büttiker probes into the channel region.
Problem Definition
On the other hand, the phonon-electron scattering is treated by Born approximation, and only the self energies involving one phonon process (absorption or emission) are considered, as higher order processes contribute less to the interaction. Since the considered device has a channel length smaller than the mean free path of the electron and operates at low voltages, we focus on the ballistic NEGF formalism in this work.
Outline of Thesis
The analytical models for graphene and graphene-based MOSFETs have been developed by many groups and have become very useful for predicting the upper limit performance. The more efficient and simpler way is to develop the quantum transport by solving the Schrödinger equation within the nonequilibrium Green's function formalism (NEGF) [101]. The main and important parameter for efficient and accurate modeling of charge transport within NEGF is the Hamiltonian matrix which can be expressed in two possible ways: 1) real-space basis (atomistic basis) and 2) mode-space basis.
NEGF Treatment of Quantum Transport
If the Hamiltonian matrix size is the total number of atoms in the device, then the solution of the NEGF equations is computationally extensive. Using the charge density, a Poisson equation is solved to obtain the self-consistent potential profile of the device. vii).
Ballistic Transport in Graphene-based Transistors
NEGF Treatment of Electronic Transport in GNR-FETs and G-FET
Thus, the non-zero block for the source self-energy matrix is the first 1×1 entry and the drain self-energy matrix is the last 1×1 entry. DS=GSΓ1,1S G+S and DD =GDΓNDx,NxG+D (2.9) The charge density at the grid sites is calculated as.
NEGF Treatment of Electronic Transport in BLG-FET and BLGNR-FET
The charge density and current from the reduced Green's function matrices can be calculated in the same way as discussed for the GNR-FET case. Furthermore, the charge and current density can be calculated in the same way as for the G-FET.
Results
Simulation of GNR-FET
2.8: (a) Transfer characteristics of the W12 AGNR-FET from our approach (solid lines) and Low's approach (circles). b) Output characteristics of AGNR-FET from our approach (solid line), Low's approach (circles) and Zhao's real-space/mode space approach (dashed line) atVGS= 0.5 V. It is noted that our approach reproduces the results excellent. both from Zhao's real-space/mode-space results.
Simulation of G-FET
The good agreement between our approach and the real-space approach is due to the constant potential around the width. It can be noted that our approach agrees well with Low's approach for all biases.
Simulation of BLGNR-FET
However, the difference in energy gap between our approach and DFT calculation is smaller compared to single-layer GNR for a width smaller than W18. For a double-layer ribbon width with energy distance above/below the critical value, the vertical electric field decreases/increases the energy distance, respectively.
Summary
Thus, the main challenge with graphene field effect transistors (GFET) for analog applications is to improve the saturation behavior in their output characteristics without significantly degrading its current levels. Therefore, a tunnel field-effect transistor (TFET), in which the S-C BTBT current is controlled by the gate voltage, may be a viable option in graphene devices to achieve better current saturation without significantly degrading the levels of his current
Device Geometry and Performance Metrics
The intrinsic performance data is calculated by running the self-consistent DC simulations discussed in Chapter 2 for G-FET. Then the intrinsic gain (AV0) and the intrinsic cutoff frequency (fT) can be calculated as.
Results
- Impact of Oxide Thickness
- Impact of Drain Underlap and Drain Overlap Lengths
- Impact of Channel and Drain Doping Concentrations
- Impact of Underlap and Overlap Lengths in a MD T-GFET
- Output Resistance and Intrinsic Gain
- C-GFET versus T-GFET
- Impact of Channel Length on Intrinsic Gain and Cutoff Frequency
In summary, the current saturation in the output characteristics of the T-GFET is possible when the C-D tunnel current becomes negligible. 3.5: (a) Output characteristics of T-GFET for different equivalent oxide thickness (EOT) at VGS = 0.4 V, and (b) Corresponding potential energy profile in the channel region at VDS = 0.6V.
Summary
Recent experimental study of 40 nm wide BLGNR-FET has reported an ON/OFF current ratio of about 3000 at room temperature [49], which is 30 times higher than the highest value reported for BLG-FET [43]. This ON/OFF current ratio with BLGNR-FET is less for switching requirements, but the manufacturing advances to produce smooth edge BLGNR with narrow width can significantly improve the ON/OFF ratio.
Digital Performance
Device Geometry and Performance Metrics
BLGNR is composed of two A-B (Bernal) stacking of armchair-edge GNRs, and the dangling bonds at the edges are assumed to be saturated with hydrogen atoms. 2.5, an air spacer of 0.5 nm is assumed between the plane connecting the center of the carbon atoms and the interface of the oxide region, but it is not shown in the scheme.
ON-state and OFF-state Performance
The reasons for small OFF current and significant ON current in BLGNR FETs are as follows. A larger energy gap reduces the OFF current and thus increases the ON/OFF current ratio to reduce the width of the device, as shown in Fig.
BLGNR-FET versus MLGNR-FET
It is observed that at Vdif f = 0 V, the ON/OFF current ratio of BLGNR devices is smaller than MLGNR devices, even though BLGNR devices have about 2x higher ON current. Therefore, BLGNR devices at wide width can provide better performance than MLGNR at high differential gate voltage.
Analog/RF Performance
Device Geometry and Performance Metrics
However, it is certainly not ideal for RF applications, as the back gate dielectric can cause higher parasitic capacitance. The BLGNR is deposited on SiO2 with a physical thickness of 2 nm, which serves as a back-gate oxide.
Output Characteristics and Intrinsic Gain
- Effect of Bias Voltage
- Effect of Underlap
Consequently, it lowers the potential energy of the channel and leads to a linear increase of the thermionic current with VDS. However, greater bottom overlap reduces the drain voltage effect in the channel region, improving current saturation for moderate VDS values.
Intrinsic RF Performance Metrics
This in turn increases the maximum intrinsic gain marginally, as observed in Fig. 4.10: Effect of underlap on BLGNR-FET. a) drain current (IDS) and (b) internal gain (AV0) as a function of VDS for different underlap lengths on the source and drain sides, at VGS =−0.2V and Vbias = 1.2 V. It is also observed that the difference ingm and the cutoff frequency between W15 and W30 units becomes smaller for more negative VGS1 values.
Summary
A TFET with BLGNR can enable a lower turn-off current, while the moderate energy gap and small effective mass with BLGNR can maintain a high turn-on current. The purpose of this work is to design and optimize a BLGNR-TFET for low voltage digital and analog applications.
Device Geometry and Performance Metrics
Digital Performance
ON-state and OFF-state Performance
This contribution from the C-D tunneling during the OFF state increases the OFF current and thus reduces the ON/OFF current ratio. 5.3(a) shows that reducing VDS is one way to improve the ON/OFF current ratio.
BLGNR-TFET Versus MLGNR-TFET
5.6(a) that narrow BLGNR devices have a higher turn-on current compared to MLGNR devices at low on/off current ratio. At very narrow width, BLGNR devices provided about 2-8× higher ON current with the same ON/OFF current ratio as MLGNR devices.
Analog/RF Performance
Output Characteristics
5.8(b) that MD+OL scheme for W30 device improves the current saturation at moderate VDS, but the quasi-linear increment is still present. This condition in turn reduces the contribution of S-C current and thus reduces the current density.
Intrinsic Analog/RF Performance Metrics
However, the peak in gm of the W15 device appears when the S-C tunnel contribution becomes significant. The smaller gds with the W15 device results in a maximum internal gain of almost 7× less than that of the W30 device.
RF Performance with Parasitics
It is observed that RF performance measurements for the W15 device are greatly degraded in the presence of the parasitic values compared to the W30 device. The inherent RF figure of merit for the W15 unit is significantly higher than the W30 unit; however, they become comparable to the worst-case parasitic values of the W30 unit.
Summary
The goals of this work are to develop a simulation tool for graphene-based devices and use that tool to understand device behavior and explore device optimization strategies. The simulation is presented for ideal graphene-based transistors and the obtained parameters are indicative only.
Future Directions
Liang, “Device physics and characteristics of graphene nanostrip tunnel FETs,” IEEE Transactions on Electronic Devices, vol. Lundstrom, “Performance Projections for Ballistic Graphene Nanostrip Field-Effect Transistors,” IEEE Transactions on Electron Devices, vol.
