Power and Area Optimized Multi-Constellation GNSS Signal Tracking System
Chandrakala R
1M.Tech Student, VLSI Design and Embedded Systems, REVA University, Karnataka, India
ABSTRACT
As the GNSS (Global Navigation Satellite System) grows, the processing capacity and area required to implement the receiver that can process all the new and legacy GNSS signals will also grow. This increases the logic area and power consumption of the underlying digital hardware -be it on a FPGA, a DSP or a combination of both FPGA and DSP platform. So, challenges arise in reducing the area and power of the hardware so that GNSS receiver can be used in low-power consuming applications such as mobile applications, portable devices, or in the systems that require low power and area efficient GNSS receivers without compromising on the position accuracy. Currently, GNSS industry is focussing on improving the position accuracy in the applications where power and area are major constraints to deploy a GNSS receiver. Hence, to meet the increased need for higher position accuracy, large number of tracking correlators is embedded in the GNSS receiver which in turn increases the area and power of the GNSS receiver. The paper proposes a novel method of tracking correlator architecture for Multi constellation GNSS receiver that is optimized for area and power when compared to that of conventional GNSS Signal Tracking System architecture. This technique is implemented and demonstrated on Virtex-7 FPGA in conjunction with the ARM Cortex A9 dual-core processor, which runs GNSS receiver software to control the correlators implemented in the FPGA.
Key Words - Area, Code Arm, Conventional GNSS Receiver, Correlator, GNSS Signal Tracking System, Integrate and Dump units, Power
1. INTRODUCTION
GNSS (Global Navigation Satellite System) is a satellite system used to identify the geographic location of a user's receiver. Satellite-based navigation systems make use a triangulation method to locate the user by using the information from a number of satellites. Each satellite transmits the carrier modulated coded signals. The receiver demodulates the carrier and then extracts signal information to provide position, velocity, and time estimates.
Global navigation satellite system (GNSS) constellations include, for example, the global positioning system (GPS) constellation, the global navigation satellite system (GLONASS) constellation, the Galileo constellation, the BeiDou navigation satellite system constellation, the Indian regional navigational satellite system (IRNSS)
constellation, the Quasi-Zenith satellite system (QZSS) constellation, and constellations of satellite based augmentation systems (SBAS) in well-defined geostationary orbits. Each satellite in the GNSS constellations continually broadcast GNSS signals that contain accurate system time and orbital position of the corresponding satellite.
With increasing global navigation satellite system (GNSS) constellations in the sky, there is an increased need for GNSS receivers that are capable of receiving and processing signals from all the GNSS constellations.
The GNSS receiver searches for a signal corresponding to a satellite in the GNSS signal and then locks onto the signal corresponding to the satellite and subsequently tracks the corresponding satellite to receive satellite information. The signal acquisition and tracking operations facilitate computation of an accurate and reliable position, velocity and time.
While conventional GNSS receivers are configured to receive GNSS signals from different GNSS constellations to provide accurate and reliable position, velocity, and time, the trade-off is the increased size of the GNSS receivers and the power consumption. Typical GNSS receivers [1] spend most of the time in the tracking operation as the GNSS receiver has to continuously track GNSS signals from satellites. To support processing of GNSS signals from different constellations, signal bandwidth requirement increases, which in turn increases the frequency of tracking system operation. This significantly increases power consumption of the GNSS receiver.
A conventional method for reducing size and power consumption of the global navigation satellite system (GNSS) receiver is by employing an application specific integrated circuit (ASIC) for processing the GNSS signals. The size and power of the ASIC is driven by the architecture of the GNSS receiver. Hence, there is a need for an architecture that reduces the area and power consumption to further reduce the cost of the ASIC.
Hence, a novel method is disclosed here to reduce the area and power consumption of the tracking channels in the GNSS receiver.
2. TYPICAL GNSS RECEIVER ARCHITECTURE
The typical GNSS Receiver [1] consists of RF Front-end, Analog-to-Digital Convertor, Baseband Processor, PVT (Position, Velocity, Time) computation Processor as shown in Fig. 1.
Figure 1: Typical GNSS Receiver Architecture
The RF Front end consists of Antenna, LNA, IF Mixer, IF Low Pass Filter IQ Modulator, Variable Gain Amplifier (Automatic Gain Control), and Crystal Oscillator.
Analog to Digital Converter (ADC) converts Analog Signal to 2-bit Digital Value.
Baseband Processor consists of acquisition and tracking systems required to demodulate and de-spread the incoming signal. In order to achieve the market demand for Time to First Fix (TTFF) and measurements accuracy, large number of correlators is embedded in acquisition and tracking systems of Baseband Processor.
The PVT computation processor operates on the correlations and measurements provided by the Baseband Processor to calculate the Position, Velocity, and Time of the user.
3. CONVENTIONAL GNSS TRACKING CORRELATOR ENGINE
The conventional Tracking system [1] comprises of large number of correlators in order to track the SVs of various constellations and mainly to achieve higher measurement accuracy to meet market demand. The Fig. 2 shows the single tracking correlator of the conventional GNSS receiver.
Figure 2: Conventional GNSS Tracking correlator
The Digitized IF (Intermediate Frequency), 2-bit output of the Analog-to-Digital Convertor is provided as input to the tracking correlator. The 2-bit Digitized IF is demodulated by passing it through the carrier mixer. The carrier mixer consists of I and Q components to employ the I-Q demodulation method. The PVT computation
processor programs the required carrier frequency to be removed. This is achieved by programming the carrier NCO (Numerically Controlled Oscillator).
The demodulated signal is passed to the code mixer in order to de-spread the signal. In order to perform fine search within a chip, the number of arms can increase. In the Fig. 2, three code arm de-spread is employed. The three arms being Early Arm, Prompt arm, and Late arm. This provides you a chip spacing of 1/3. The LFSR based code generation method is employed to generate the required code at the chipping rate programmed to the Code NCO by the PVT computation processor.
The de-spread signal is further integrated to accumulate the correlation values required for the PVT computation processor to track the satellite. The integration period can vary up to 0.5*data period.
The TABLE 1 provides the resource consumption of the conventional GNSS Tracking Correlator Engine as the number of channels increases.
Table 1: Block Level Resource Computation of Conventional GNSS Tracking Correlator Engine
Blocks Resource Utilization
Carrier NCO 1*N
Sine and Cosine Mapped LUTs 2
Carrier Mixers (I and Q) 2*N
Code NCO 1*N
Code Generator 1*N
Code Mixers m*N
Code Shift register (p-width)
1*N
Integrate and Dump units (I and Q)
2IQ*m*N
Integrate and Dump Register outputs 2IQ*k*m*N
Coherent Results Memory/Registers to PVT computation processor 2IQ*(k*m)*N
N represents number of channels;
m represents number of code arms supported by each tracking channel;
p represents the width of the Code Shift Register chosen depending on the system requirement on chip spacing and chip range to be supported by the GNSS Signal Tracking System;
k represents the width of the accumulator that depends on the integration time duration and carrier mixer output width
k = Wcm + LOG2 (Ns) (1)
Where,
Wcm is the carrier mixer output width
Ns is the number of samples to be accumulated in the pre-defined integration period
4. PROPOSED AREA AND POWER OPTIMIZED DESIGN OF GNSS TRACKING CORRELATOR ENGINE
From TABLE 1, it can be seen that as the number of tracking channels increases, the resources used in the GNSS Signal Tracking System also increases. It is desirable to increase the number of tracking channels where there is a necessity to provide highly précised measurement accuracy [2].
Increase the resource consumption by the GNSS Signal Tracking System increases the area of the GNSS receiver. As the area increases, the leakage power consumed by the Tracking system also increases. As per ASIC industry standards, the leakage power variation from typical to fast-fast process is 28 times i.e. leakage power at fast-fast process is 28 times than that of typical process. The increase the area consumption hits the leakage power itself. In the consumer electronics like mobile applications, smart watches, and other portable devices require miniature sized devices consuming less area and power.
Hence, the goal is reduce the resource consumption of each tracking correlator that in turn reduces the area and hence the power of the GNSS Signal Tracking System.
In the conventional GNSS Receiver, if there is N number of tracking correlators, there would be N number of Integrate and Dump units for each code arm that consumes more power and area. The scope is to optimize the logic of Integrate and Dump units in each correlator and reduce the impact of scaling factor ‘N’ on Integrate and Dump units which saves significant amount of area and in turn reduce the power consumption.
The Fig. 3 represents the block diagram of the Area and Power Optimized GNSS Tracking Correlator engine.
Figure 3: Optimized GNSS Correlator Engine in Tracking System
The TABLE 2 provides the resource consumption of the conventional GNSS Tracking Correlator Engine as the number of channels increases.
Table 2: Block Level Resource Computation of Conventional GNSS Tracking Correlator Engine
Blocks Resource Utilization
Carrier NCO 1*N
Sine and Cosine Mapped LUTs 2
Carrier Mixers (I and Q) 2*N
Code NCO 1*N
Code Generator 1*N
Code Mixers m*N
Code Shift register (p-width)
1*N
Integrate and Dump units 2IQ* ( l*N+1 )*m
(I and Q) (l << k)
Integrate and Dump Memory Components 2IQ*l*m*N Coherent Results Memory to PVT computation processor 2IQ*k*m*N
N represents number of channels;
m represents number of code arms supported by each tracking channel;
p represents the width of the Code Shift Register chosen depending on the system requirement on chip spacing and chip range to be supported by the GNSS Signal Tracking System;
l represents the width of the small adders required in the region of the optimized block. Note that l is at least 0.4 times less than k.
k represents the width of the accumulator that depends on the integration time duration and carrier mixer output width
k = Wcm + LOG2 (Ns) (2)
Where,
Wcm is the carrier mixer output width
Ns is the number of samples to be accumulated in the pre-defined integration period
The proposed area and power optimized tracking correlator engine has significant area saving in terms of number of integration and dump units used. And as the number of channels increases, the saving ratio increases.
Further by employing the technique with the memory further saves the registers and hence the area. This is because the registers (flip-flops) consume more area and power when compared memories in ASIC. Further clock tree power is also saved.
Hence this design method provides efficient area and power utilization.
5. IMPLEMENTATION OF PROPOSED AREA AND POWER OPTIMIZED DESIGN OF GNSS TRACKING CORRELATOR ENGINE
The optimized tracking engine is implemented in the system consisting of RF Front End, 2-bit ADC, and Baseband processor implemented in VIRTEX-7 FPGA (Field Programmable Gate Array).
Analog to Digital Converter (ADC) converts Analog Signal to 2-bit Digital Value. It supports both Offset Binary Encoding and Two’s Complement Encoding. The ADC sampling clock is 45 MHz.
ARM Cortex A9 dual-core processor controls the operations of Baseband Processor by programming the tracking system parameters through AMBA AHB interface.
Figure 4: GNSS Receiver Architecture for proposed method
With the 2-bit incoming IF, the resource utilization in tracking correlator of single channel is provided in the TABLE 3:
Table 3: Resource Utilization Comparison in Virtex-7 FPGA Resource
Utilization (per channel)
Optimized Tracking System
Conventional Tracking System
Area Saving Percentage
Flip-Flops 1885 3281 42 %
LUTs
(Look Up Table)
1806 3857 53 %
Memory (RAMB36)
4 1 Increased by 3 in
number
From the TABLE 3, it can be seen that the number of flip-flops inferred in the proposed design method is 0.57 times that of the conventional GNSS receiver. The number of LUTs inferred is 0.46 times that of the conventional GNSS receiver.
Though the number of memories have increased, its increase is not significant when compared to the area saving of Flip-Flops and LUTs as the memories designed for FPGA/ASIC are highly area and power optimized. Hence, saving the flip-flops and LUTs significantly saves the area. As an offshoot, clock tree power and leakage power is also reduced.
6. RESULTS AND DISCUSSION
The proposed GNSS Signal Tracking System is tested in simulation and on-board for its functionality. The results are captured for the On-Target testing.
The Fig. 5 provides the code triangle of the GPS L1 C/A achieved with the optimized tracking Engine
Figure 5: Code Triangle of GPS L1 C/A
The impact of the new architecture on the C/N0 of the GNSS signal is as shown in the Fig. 8.
Figure 6: Impact on C/N0 (dB/Hz)
With the area and power optimized GNSS Signal Tracking system, the GPS L1 C/A, GLONASS constellation SVs are continuously tracked as shown in Fig. 9 and Fig. 10.
Figure 7: C/N0 of SVs in GPS L1 C/A
It can be seen that all the GNSS tracking channels programmed for GPS L1 C/A are providing the same C/N0. It can be concluded that there is no compromise among the SVs processed in different tracking channels with this novel method of implementation.
Figure 8: C/N0 of SVs in GLONASS
The variation in C/N0 among different tracking channels for GLONASS constellation is due to variation in the RF Front-End Analog Filter responses as the GLONASS employs FDMA technique and each SV is associated with different center frequency.
7.
CONCLUSION
A novel method to reduce the area and power consumption of the GNSS Signal Tracking System without compromising the C/N0 (at a top level, it is an indication that the position accuracy is also not compromised) is proposed, implemented, and tested on FPGA platform using live GNSS signals. The proposed method has significant area saving in terms of number of integration and dump units used. The percentage of area saving for registers is 42% and that of LUTs is 53%. The benefit will increase with the increase in the number of tracking channels. Further, by employing the technique with the memory further saves the registers and hence the area as the registers (flip-flops) consume more area and power when compared to that of memories in ASIC/FPGA. As an offshoot, reduction in number of registers also reduces the clock tree power as the clock path length is shortened.
As demonstrated, the proposed novel method can be deployed in the GNSS receivers that make use of FPGAs because of the abundance of memory blocks in the FPGAs. Every FPGA device comes with a set of memory blocks, whether they are required or not. If the receiver architecture can make use of the memories in the FPGA then the other logic resources (flip-flops and LUTs) required can be reduced. Therefore, the novel method enables the designer to select a smaller FPGA which in turn saves not only the area and power consumption but also the cost.
8. AKNOWLEDGEMENTS
The author would like to thank Accord Global Technologies Solutions Private Limited, Bangalore for providing the infrastructure and Dr. Naveen GS, Accord Global Technologies Solutions Private Limited and Dr. S. N.
Prasad for providing the guidance in carrying out this paper work.
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