A Study of Implementing Custom Application on Zynq AP SoC using Xillybus IP Core

(1)

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE)

________________________________________________________________________________________________

ISSN (PRINT) : 2320 – 8945, Volume -2, Issue -5,6 2014 35

A Study of Implementing Custom Application on Zynq AP SoC using Xillybus IP Core

1Bharat M Kambalur, ²Krishna Kumar K, ³Kishan S Athrey

1,2,3Undergraduate Student, Dept. of Electronics and Communication

1,2,3BMS College of Engineering, Bangalore, India

Email: ¹[email protected], ²[email protected], ³[email protected]

Abstract—In this paper, an overview of Zedboard development board and Zynq AP SoC is given. The internal architecture of the SoC is explained. The AXI bus architecture and operations are described. The use of Xillinux operating system and Xillybus IP core are also discussed. The process of implementing a custom application to run on this platform is detailed. Possible applications for this platform are mentioned.

Keywords— Zynq, Zedboard, Xillybus, Xillinux, PS, PL, SoC, AXI, IP Core, Embedded Linux

I. INTRODUCTION

The use of embedded operating systems such as Linux in a product or an end application is growing every day.

Using embedded operating systems enable us to leverage the various tried and tested functionalities such as Network connectivity, Peripheral interfacing, Memory management, etc. With this growing interest in embedded operating systems, a simple yet powerful system is required for easy and fast R&D process. One such platform is Zedboard. This is a development board built around a Zynq All Programmable System on Chip (AP SoC) device. The SoC comprises both a dual core ARM processor and a FPGA fabric. The further sections explain these in greater detail.

II. ZEDBOARD HARDWARE OVERVIEW

Zedboard stands for Zynq Evaluation and Development board. It is based on Xilinx Zynq-7000 series AP SoC.

The Zynq chip consists of two major sections, the processing system (PS) and the programmable logic (PL) [1]. It packs the power and performance of a processor and flexibility of design of an FPGA. This platform provides software (PS), hardware (PL) and Multiplexed I/O (MIO) programming flexibility. Also, the PS and PL can function independently.

Processing System

The processing system consists of Dual core ARM Cortex – A9 processor. It is an application grade processor capable of running operating systems such as Linux, RTOS, embedded windows etc. Each core of the PS is associated with NEON and FPU engine. It has

Level 1 cache memory of 32KB of data and 32KB of instruction, Level 2 cache of 512KB of shared memory between the two cores. The processor can be clocked up to an operation speed of 1GHz. The cores of the processor can be accessed in three different modes:

 Symmetrical multiprocessing mode (SMP) – Single OS running on both cores

 Asymmetrical multiprocessing mode (AMP) – Each core with different OS

 Uni-Processing mode (UP) - Only single core can be used

The Zedboard comes with a built in DDR3 RAM of 512MB memory. The Zedboard also features a 4-bit SPI serial NOR flash memory of size 256Mb. This non- volatile memory is shared between the PS and PL subsystems. It supports speeds up to 400Mbps and hence it is suitable for storing boot loaders and kernel of an OS, which is necessary to boot up the processing system. The PS comes with 54 dedicated peripheral I/Os. The I/Os are multiplexed and consists of dual channel SPI, I2C, CAN, UART, etc. [2].

A. Programmable logic

The programmable logic is based on Artix-7 FPGA fabric for minimised power consumption and Kintex-7 fabric for improved performance. PL is capable of massive parallel processing as it contains around 900 DSP blocks [3]. This makes it ideal for signal processing. The major components of PL block are Logic cells, BRAM, DSP blocks, clock resources etc.

The Zedboard comes with extended multiplexed I/Os, which are connected to PL, enables extensive use of PL for various applications. It comes with analog mixed signal capabilities, as it consists of dual 12-bit ADC and can be used in interfacing various sensors as per the application.

III. AXI BUS

AXI stands for Advanced extensible Interface. This protocol is a part of the Advanced Microcontroller Bus Architecture (AMBA) standard. This standard is used in Zynq SoC. This standard consists of one primary

(2)

________________________________________________________________________________________________

controller which acts as the master, and one or more slave peripherals. The memory mapped master and slave devices can be connected together using a structure called an interconnect block. The AXI interface uses five channels through which the master communicates with its slaves. Hence read and write processes can run simultaneously over the bus. The five channels are:

 Read Address Channel

 Write Address Channel

 Read Data Channel

 Write Data Channel

 Write Response Channel

The read process utilizes the read address channel and the read data channel. The address is sent by the master interface over the read address channel to the slave interface. In response to this, the slave interface sends the corresponding data over the read data channel to the master. Fig. 1 shows an overview of the read process.

The write process utilizes three channels – write address channel, write data channel and the write response channel. The Master interface sends the address to which the data is to be written and corresponding data.

On successful write at the slave interface, the slave sends a response over the write response channel to indicate the same. Fig. 2 shows an overview of the write process.

The PL can access the DDR memory and on chip memory directly through the AXI interconnect without the intervention of the PS. The PS can be connected to PL peripherals through the AXI interconnects which serves as a bridge between them [4].

Fig. 1. Overview of the Read Process

Fig. 2. Overview of the Write Process

IV. XILLYBUS IP CORE

Xillybus is a Direct Memory Access (DMA) based solution for data transfer between the FPGA (PL) and a host platform running Linux (PS). The Xillybus IP core can be implemented in the PL part of the ZYNQ SoC for creating a communication link between the PS and PL sections. The host driver generates device files that behave like named pipes. They are opened, read from and written to just like any file, but behave much like pipes between the host and the PL. The Xillybus stream is designed to work well with high-rate data transfers as well as single bytes arriving or sent occasionally. The IP core achieves its functionality by utilizing the AXI interconnects. A functional overview of the Xillybus IP core is shown in Fig. 3.

The Xillybus IP Core is compatible with the Xillinux 1.3 release [5]. This is an operating system based on Ubuntu 12.04 which can be ported for the Zynq target. Xillinux, which is running on the PS, acts as the host to the Xillybus IP core implemented in the PL.

Fig. 3. Overview of Xillybus IP Core

V. IMPLEMENTATION

The Xillybus IP core is implemented in the Programmable Logic. The Linux kernel acts as a link between the operating system and the IP core. The Linux operating system creates device driver files which are present in the ‘\dev\’ folder. There are separate device driver files for different operations as shown in Table 1 [6]. Each device file has different characteristics like speed, bandwidth and data width. Writing to these device files on the Linux host gets reflected in the Programmable Logic. The read operation reads from the FIFO and the same is stored in the corresponding device file [7].

A custom application which is run on the Linux OS can interact with the custom logic implemented in the FPGA by writing to or reading from these device files. A complete overview of the entire process is shown in Fig.

4.

(3)

________________________________________________________________________________________________

TABLE I. DEVICE DRIVER FILES

Name Direction Data

Width

Bandwidt

h Details

xillybus_

read_32

Upstream (FPGA

to host) 32 bits 195 MB/s

Data Acquisition

/ Playback (100 ms) xillybus_

write_32

Downstream

(host to FPGA) 32 bits 195 MB/s

Data acquisition

/ playback (100 ms) xillybus_

read_8

Upstream (FPGA

to host) 8 bits 1 MB/s General Purpose xillybus_

write_8

Downstream

(host to FPGA) 8 bits 1 MB/s General Purpose xillybus_

mem_8

Upstream (FPGA to host) Downstream (host to FPGA)

8 bits 102.4 kB/s

Address / Data Interface (5

address Bits)

Fig. 4. Architecture of Implementation

VI. APPLICATION

Softwares such as GNU Radio can be run in the Linux environment. This application interacts with the hardware logic implemented on the FPGA through the Xillybus IP core. Different custom logic designs can be used for different signal processing applications performed in the GNU Radio software. Other hardware projects such as realizing a signal generator or an oscilloscope can be implemented. Here, the monitor interfaced with the Zynq SoC acts as the display. A custom application running in Linux can be used to

interact with the hardware [8]. A similar approach can be extended to various other applications.

VII. ACKNOWLEDGMENT

The authors would like to thank Center for Development of Telematics (C-DOT), an Indian Government owned Telecommunications technology development center, for providing an opportunity to work with this development board. The authors also wish to thank various employees who have guided and aided them in numerous ways.

REFERENCES

[1] D. Dhanalaxmi and V. Roopa Reddy, 'Implementation of Secured Data Transmission System on Customized Zynq SoC', International Journal of Science and Research, vol. 3, no. 8, pp. 1980-1987, 2014.

[2] Zedboard Hardware User's Guide, Avnet Electronics Marketing, 2012. URL : http://zedboard.org/sites/default/files/ZedBoard _HW_UG_v1_1.pdf

[3] C. Dobson, 'An Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applications', Masters Dissertation, Virginia Tech, 2014.

[4] AXI Reference Guide, Xilinx, Inc., 2011,

UG761URL :

http://www.xilinx.com/support/documentation/i p_documentation/ug761_axi_reference_guide.p df

[5] Getting started with Xillinux for Zynq-7000

EPP, Xillybus Ltd. URL :

http://xillybus.com/downloads/doc/xillybus_get ting_started_zynq.pdf

[6] The guide to defining a custom Xillybus IP

core, Xillybus Ltd. URL :

http://xillybus.com/downloads/doc/xillybus_cus tom_ip.pdf

[7] Xillybus getting started linux, Xillybus Ltd.

URL :

http://xillybus.com/downloads/doc/xillybus_get ting_started_linux.pdf

[8] Xillybus host application programming guide for Linux, Xillybus Ltd. URL : http://xillybus.com/downloads/doc/xillybus_ho st_programming_guide_linux.pdf

