Introduction 1
Background 2
- Power quality 2
- Solutions to power quality problems 4
- Power filter topologies 4
- Voltage source converters 6
- Control strategies 7
However, the apparent power value of the active power series filter may increase in case of voltage compensation. The active series filter is a combination of the active series filter and the active shunt filter.
Objective 8
The FSMD architecture is based on a finite state machine (FSM) used to control the DATAPATH. The advantages of a digital controller over conventional controllers such as PI controllers are that FPGAs provide reconfigurable hardware designs, low-cost development (reprogrammability), FPGAs can process information faster than general-purpose DSPs, selectable bit widths for data registers . based on the needs of the application, designed in a hardware description language (VHDL or VERILOG), the controller becomes independent of the process technology, can work with imprecise inputs, can handle non-linearity, load disturbances, etc.
Thesis Outline 9
Therefore, the source current (i.e. the real power drawn from the source) must be increased, while a larger DC capacitor voltage than the reference voltage tries to decrease the reference source current. It is implemented by a data flow graph (DFG). The DFG is implemented using FSMD architecture for FPGA implementation. The supply voltage is balanced and is defined as vs(t) Vmsin t. The measurement of the three-phase instantaneous supply voltage is shown in Figure 6.1.
In Figure 6.1, the values of Iref_num and Iload_num are loaded to the corresponding memory location before state-1, which is written in the VHDL code. The calculation of the error Iinj_num will take 29 states, from S0 to S28, as shown in Figure 6.13 (a-c). The comparator together with the. The APF provides the compensating current shown in Figure 6.7. The source current after compensation is shown in Figure 6.8 and Figure 6.12, indicating that the current becomes sinusoidal.
Shunt Active Power Filter 10
Basic compensation principle 11
The peak value of the reference current Isp can be estimated by controlling the DC side capacitor voltage. This algorithm facilitates the derivation of id-iq (rotating current coordinate) from three-phase stationary coordinate load current iLa, iLb, iLc. 3.2) The d-q transformation output signals depend on the load current (fundamental and harmonic components) and the performance of the Phase Locked Loop (PLL). The hysteresis band current control for active power filter is used to generate the switching pattern of the inverter.
It turns out that the same idea can be used when designing an ALU circuit as when designing an adder/subtractor combination circuit. The primary inputs will be modified accordingly according to the operations performed before they are passed to the full adder. The FSMD consists of a control unit and a data path, where the data path operates under the control of a control unit (FSM). The FSM provides control signals to the data path, and the data path provides status signals to the FSM. This conforms to IEEE standards. The digital controller vhdl code written in xilinx is transferred to the FPGA for hardware implementation, and the gate pulses for phase A are shown in Figure 6.15 (a-b). Similarly, pulses for phase B and phase C are obtained.
Estimation reference current 11
Estimation source current 12
Role of DC side capacitor 13
At steady state, the actual power supplied by the source should be equal to the actual power requirement of the load plus a small amount of power to compensate for losses in the active filter. However, when the load condition changes, the actual power balance between the network and the load will be disturbed. To maintain satisfactory operation of the active filter, the peak value of the reference current must be adjusted to proportionally change the actual power drawn from the source.
This real power charged/discharged by the capacitor compensates the real power consumed by the load. If the DC capacitor voltage recovers and reaches the reference voltage, the real power supplied by the source is assumed to be equal to that consumed by the load again. A smaller DC capacitor voltage than the reference voltage means that the real power supplied by the source is not sufficient to supply the load demand.
Selection of Lc and Vdc,ref 14
Design of DC side capacitor (Cdc) 14
The basic structure of SRF methods consists of direct (d-q) and inverse (d-q)-1 Park transformations, as shown in Figure 3.1, which allows the evaluation of the specific harmonic component of the input signals [15]. Von Neumann's model of a computer, pictured in Figure 4.1, consists of four main components: input, output, memory, and CPU (central processing unit). The control block is implemented using a PI-controller based on the recurrent equation 5.3.1 and shown in Figure 5.3. Here, 16-bit signed integer bit encoding is used with thousandths precision.
Synchronous Reference Frame (SRF) Theory and Hysteresis Current Controller 15
Basic Principle 15
SRF Controller Implementation 15
The transformation of the reference frame is formulated from the three-phase stationary system a−b−c to the rotational coordinate system of the direct axis (d) and the quadratic axis (q). In a-b-c, the stationary axes are 1200 apart, as shown in Figure 3.1. 3.2) The output signals of the d-q transform depend on the load current (fundamental and harmonic components) and the performance of the phase-locked loop (PLL). The id-iq current is passed through a low-pass filter (LPF) to filter out the harmonic components of the load current, which only passes the fundamental frequency components.
The PI controller is used to eliminate the steady-state error of the DC component of the d-axis reference signals. The capacitor voltage on the DC side of the PWM voltage source converter is measured and compared to the desired reference voltage to calculate the error voltage. This error voltage is passed through a PI controller whose propagation gain (KP) and integral gain (KI) are 0.1 and 1, respectively.
Hysteresis Current Controller 17
Conventional hysteresis current control controls the PWM voltage source inverter by comparing the current error e(t) with fixed hysteresis bands. If the fault current exceeds the upper limit of the hysteresis band, the upper switch of the inverter arm is turned off and the lower switch is turned on. If the fault current exceeds the lower limit of the hysteresis band, the lower switch of the inverter arm is turned off and the upper switch is turned on.
The variation in the switching frequency affects the performance of the current regulator, both in terms of harmonics and the maximum switching frequency. Whenever the current error e(t) exceeds an outer hysteresis limit, the inverter output is set to an active positive or negative output to force a reversal of the current error. Similarly, when the current error reaches an inner hysteresis limit, the inverter output is set to zero and the current error is forced to change direction without reaching the next outer limit.
Adaptive hysteresis current controller 20
The conventional power circuit of the voltage source converter-based active power filter connected to the point of common coupling, as shown in Figure 6.1. This paper presents the design and implementation of a three-level hysteresis current control scheme for three-phase four-wire active power line conditioners. 19] W.Diyun, C.Yanbo, K.W.Cheng,"Design and Implementation of a Shunt Active Power Filter for Three-Phase Four-Wire Systems",IEEE Conf.
FSMD Architecture 23
Finite State Machine 24
DATAPATH Description 25
The DATAPATH includes (1) functional units such as adders, shifts, multipliers, ALUs, and comparators, (2) registers and other memory elements for temporary storage of data, and (3) buses and multiplexers for transferring data between various components of the DATAPATH. For DATAPATH to function properly; appropriate control signals must be asserted at the right time. Control signals are required for all select and control lines for all components used in the DATAPATH.
This includes all the select lines for multiplexers, ALU and other multi-operation functional units, all the read/write enable signals for registers, address lines for memory and enable signals. The operation of the DATAPATH is determined by which control signals are asserted and at what time. In return, the DATAPATH must provide status signals back to the control unit in order for it to function correctly.
Description of RAM, ALU, REGISTER, MULTIPLEXER 25
- Random Access Memory 25
- Arithmetic and Logic Unit 25
- Shift Register 26
- Multiplexer 26
The performance of the adaptive hysteresis current controller and the current-controlled shunt active power filter with fixed hysteresis is verified with the simulation results. 13] Charles.s,G.Bhubaneswari,”Comparisons of Three Phase Shunt Active Power Filter Algorithms”,IJCE,vol.2,no.1,February 2010. 14] S.Rahmani,N.Mendalek,K.Al-Haddad ,Experimental design of a nonlinear control scheme for three-phase,shunt active power filter,IEEE Trans.
Pitel “Analysis and Design of a New Active Power Filter to Cancel Neutral Current Harmonics in Three-Phase Four-Wire Power Distribution Systems,” IEEE Trans. 26] M.Kale,E.Ozdemir,"An Adaptive Hysteresis band Current Controller for Shunt Active Power Filter",Electrical Power Systems Research 74,pp. 28] S.Gautam,R.Gupta,”Three level inverter based active shunt power filter using generalized hysteresis current control method”,IEEEconf.October 2010.
CONTROLLER DESIGN 28
FSMD Model 28
So far we have learned how to design the DATAPATH and control unit separately. This build method uses the FSM+D model (FSM plus DATAPATH) since FSM and DATAPATH are built separately. The FSM and DATAPATH are linked together in an enclosing entity module using control and status signals.
The advantage of using the FSM+D model is that we have complete control over how the control unit and DATAPATH are constructed. However, instead of manually constructing the DATAPATH as a separate module, all DATAPATH operations are embedded in the FSM entity using the built-in VHDL operators. Please note that if we write VHDL code for a controller using FSM+D model.
HCC Block Description 29
Digital Controller Design and Operation 30
- Regulator Description 30
- Behavioral Description 31
- FSMD Architecture 31
17] M.Isabel,M.Montero,E.R.Cadaval,F.B.Gonzalez “Comparison of control strategies for shunt active power filters in three-phase four-wire systems” IEEE Trans. 22] L.A.Moran et al, "A Fixed Switching Frequency Operating Three-Phase Active Power Filter for Reactive Power and Current Harmonic Compensation", IEEE Trans.on Indus.Elect.vol.42,pp. 25] J.Zeng,Chang.Yu et al, "A new hysteresis current control for constant frequency active power filter", Power Systems Research 68, pp.75-82.
1] Saswat Kumar Ram, KauppananP, K.K.Mahapatra “Active power filter for harmonic compensation based on three-level hysteresis controller” IEEE Conf, ICETECT, pp.407-412, MARCH 2011. 2] Saswat Kumar Ram, S.R.Prusty, K.K.Mahapatra, B.D. Subudhi “Performance Analysis of Adaptive Bandpass Hysteresis Current Regulator for Shunt Active Power Filter” IEEE Conf, ICETECT, pp.425-429, MARCH 2011.
Simulation Results 34
Conclusion and Scope for the Future Work 44
