Verification of I²C Single-Master Multiple-Slave Bus Controller using System Verilog

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International Journal of Electrical, Electronics and Computer Systems (IJEECS)

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ISSN (Online): 2347-2820, Volume -2, Issue-4, 2014 26

Verification of I²C Single-Master Multiple-Slave Bus Controller using System Verilog

1Yashaswini Pandit, ²Manoj P B M. Tech student¹, Associate Professor²

Email: ¹[email protected], ²[email protected]

Abstract- It verifies the serial data communication using

I²C (Inter-Integrated Circuit) master-slave bus controller in System Verilog. One master and multiple slaves’

implementation is performed using Verilog RTL coding.

Verification of I²C controller that transmits and receives the data to slaves is performed by simulation using System Verilog , simulated using QuestaSim tool. System Verilog complex simulation environment coding is done to verify design in simulation. The module was designed in Verilog HDL and simulated in QuestaSim 6.4c.It can be used to interface peripherals like radio, TV, cell phones, DVD, PDA etc.

Index Terms - Modelsim altera 6.6d, QuestaSim 6.6d, System Verilog

I. INTRODUCTION

The I²C (Inter-Integrated IC) bus developed by Philips company, is a simple bidirectional serial bus that supports multiple masters and slaves. It uses only two lines: Serial bidirectional data line (SDA) and Serial bidirectional clock line (SCL).Within I²C bus specifications, a standard mode with a max clock rate of 100k Hz and a fast mode of max clock rate of 400k Hz are defined. The size of IC has been decreased over the years, so there is a need for less number of pin connections for serial data transfer.

Since there is a progress in VLSI technology, billons of transistors have been integrated into a single chip (SoC).Due to this verification takes an important place and more than 70 percent of time is been spent on functional verification.

In this paper, I²C bus is used for communication, which is been used for interfacing peripherals, since it‟s the well know standard bus over 20 years of existence and it‟s been used as a standard bus by many industries. I²C bus is been implemented with single master and multiple slaves and its functionality is been verified before the design is been sent to the fabrication process. Verification of single master and multiple slaves is been performed using System Verilog.

Fig. 1. Block Diagram.

II. PROPOSED WORK

A.I²C Protocol

The I²C-bus is a bidirectional serial bus which supports any IC fabrication process (NMOS, CMOS, bipolar).The transaction is always initiated by master.

It uses two wires for communication:

SDA: Transmission of any data takes places through this line.

SCL: It is a clock line which is responsible for controlling and synchronizing the communication.

A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. Clock and reset are the input lines used to initiate the bus controller process. The R/w signal is given as an input to indicate whether master or slave acts as a transmitter in the data transmission.

B.Start and Stop Conditions

START: SCL is high and SDA will take a transition from High to Low shown in Fig 2.1(a).

STOP: SCL is high and SDA will take a transition from Low to High shown in Fig 2.1(b).

IDLE: Both SDA and SCL are high.

Fig. 2.1 (a) “START” Sequence. (b) “STOP” Sequence

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C. Acknowledgement

In I²C an ACK needs to be sent by Receiver shown in Fig.2.2. After transmitting the address byte, master pulls the SDA line in high impedance state, thus allowing the slave to respond with an acknowledgement which it does by pulling the SDA line low. After releasing the SDA line master generates the clock to read the ACK bit. If ACK is received master can proceed with read/write bit operation.

If the transmitted address does not match any of these slaves present shown in Fig.2.3, none of the slaves would pull down the SDA and the line remains high.

Master interprets this as NACK. If NACK is received master can issue STOP command or reissue the START command.

Fig. 2.2 ACK received on the SDA line

Fig. 2.3 NACK received on the SDA line.

D. Serial Data Communication

There are two modes of transmission: Master Transmission mode and Master receiver mode.

In the master transmission mode [1], shown in Fig 2.4, master begins the communication by initiating the start condition followed by sending 7-bit slave address with MSB bit is sent first. The direction bit (R/W) with W=0 is specified. This is then followed by the Acknowledgement bit specified by the receiver. The transmitter then sends the register address to the slave which sets the register pointer on the particular slave.

The master then sends the data acknowledging each byte of data that is received. The master then sends the stop condition to terminate the data write.

Fig.2.4 Master Transmission Mode

In the Receiver mode shown in Fig 2.5, data is received from slave transmitter mode. After the start condition, master sends the slave address followed by the direction bit (W=1) to indicate it as read mode. The

slave device sends an acknowledge bit after receiving address and direction bit. A repeated start condition (Sr) is carried out with 7 bit slave address with R=1, acknowledging it. The slave receives the data of 7 bits with acknowledging each byte sent. Finally when all bits have been received stop condition is initiated to stop the communication.

Fig.2.5 Master Receiver Mode

III. SIMULATION RESULTS

Fig 3.1 shows the Modelsim expected simulation result for clock generation. Fig 3.2 shows the expected results for Write operation. Fig 3.3 shows the expected result for Read operation.

Fig.3.1 Clock Generation.

Fig. 3.2 Simulation result of Master for Slave1

Fig.3.3: Simulation result for Slave1

Fig 3.4 Simulation result of Master for Slave 2

Fig 3.5 Simulation result for Slave 2

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Fig 3.6: Simulation result of Master for Slave 3

IV. VERIFICATION [6]

As the complexity of the SoC design is increasing, well structured verification environment is important. There are many verification tools and methods, but simulation is the fundamental method used for functional verification. System verilog is getting more popular.

Fig 4: I²C verification environment architecture [10]

The verification environment architecture [10] for I²C protocol is shown in Fig 4.

There are two levels of verification in SoC namely IP level verification

Top level verification.

The purpose of verification engineer is to be sure that device can accomplish the task correctly, according to the specifications. The goal of hardware design is to create a device that performs a particular task, based on a design specification.UVM method is used in verification. Different principles have been used like Functional coverage, constrained random stimulus etc and coverage results can be obtained once it‟s been verified.

A. Expected Result

Fig 4: Coverage result of I2C simulated in QuestaSim tool.

The above verification coverage result is as shown above. By using the randomization process we can see that, different random values in Hex is been taken by driver and simulated which then is run and „1„is achieved which means that all the test data is passed and hence we have achieved verification process successfully.

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CONCLUSION

In this paper I²C can be verified by system verilog using QuestaSim 6.4c tool, to check whether Master is sending all the data and receiver is receiving all the data sent by the Master in simulation and demonstrates the upto to date Software implementation results of I²C Master Controller that transmits and receives data to and from the Slave, so that low speed peripheral devices can be interfaced using I²C bus protocol as master. By using the verification Environment the DUT is verified for its functionality.

REFERENCES

[1] Bollam Eswari, N.Ponmagal, K.Preethi, S.G.Sreejeesh “Implementation of I²C master bus controller on FPGA” IEEE 2013.

[2] I²C Bus Specification, Philips Semiconductor, version 2.1, January 2000.pp. 9-11

[3] Samir Palnitkar, “Verilog HDL - A guide to Digital Design and Synthesis”, 2nd edition, prentice hall PTR, Feb 23, 2003.

[4] ”Universal Serial Communication interface”- I²C mode, Texas Instruments, SLAU208 Revised February 2013,pp 5-6.

[5] Verilog® HDL Quick Reference Guide, IEEE Standard 1364-2001.

[6] AN10148 I2C Manual, Philips Semiconductor, Nov 2004.

[7] Chris Spear, System Verilog for Verification,2^nd edition, a Guide to Learning the Testbench Language Features, Springer publications.

[8] I²C tutorial “Using the I²C Bus”, http://www.robotelectronics.co.uk/acatalog/I2C _Tutorial.html.

[9] Purvi Mulani, Jignesh Patoliya, Hitesh Patel, Dharmendra Chauhan, “Verification of I²C DUT using System Verilog” IJAET, Vol.I, Issue III , Oct.-Dec.,2010, pp 130-134

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