View of AN ANALYTICAL APPROACH FOR VLSI DESIGN OF LOW POWER APPLICATION

(1)

Vol.03, Issue 09, Conference (IC-RASEM) Special Issue 01, September 2018 Available Online: www.ajeee.co.in/index.php/AJEEE

1

AN ANALYTICAL APPROACH FOR VLSI DESIGN OF LOW POWER APPLICATION Sandeep Kumar Dinkar

Associate Professor Laxmi Devi Institute of Engineering and Technology, Alwar, RTU, Kota Gautam Kumar, Student

Abstract - Simple to-computerized converters (ADCs) are key structure squares and are right now received in numerous application fields to improve advanced frameworks, which accomplish better exhibitions with deference than simple arrangements. Application, for example, remote correspondence and advanced sound and video have made the requirement for cost-effective information converters that will accomplish higher speed and goals. Across the board utilization presents incredible significance to the structure exercises, which these days to a great extent adds to the creation cost in coordinated circuit gadgets (ICs). Different instances of ADC applications can be found in information procurement frameworks, estimation frameworks and computerized correspondence frameworks additionally imaging, instrumentation frameworks. Since the ADC has a persistent, unending – esteemed sign as its information, the significant simple focuses on the exchange bend x-pivot for an ADC are the ones that comparing to changes in the computerized yield word. These information changes decide the measure of INL and DNL related with the converter. Consequently, we need to considered all the boundaries and improving the related presentation may fundamentally diminish the mechanical expense of an ADC fabricating process and improved the goals and configuration uncommonly power utilization . The paper presents a plan of 4 piece Pipeline ADC with low force dispersal executed in <0.18µm.

Keyword: ADC, PIPELINE, CMOS 1. INTRODUCTION

ADC is the key parts in correspondence and video framework. With advancement of these gadgets framework, high goals and fast ADCs are turning out to be increasingly significant. Fast low-power Analog-to-Digital converters (ADCs) are the basic structure obstructs for present day correspondence and sign handling frameworks. They are the interface between the simple and advanced sign preparing. Since the mid-1970s. ADCs have been generally planned utilizing coordinating, progressive estimate, blaze, and delta-sigma strategies. All the more as of late, there has seemed another class of ADC with a design known as pipeline, which offered an appealing blend of fast, high goals, low force dissemination and little bite the dust size.

The pipeline ADC, in this manner, turned into the ideal answer for present low force applications, for example, a remote correspondence framework. A proceeded with scan for circuit structures and methods empowering ADCs to acquire higher speed and goals with littler chip region and lower power scattering, in this manner, is essential.

The pipeline simple to-computerized converter (ADC) is a promising topology for fast information transformation with reduced zone and proficient force scattering. Its speed of activity far outperforms that of sequential based structures, for example, progressive estimate or cyclic converters, while its kick the bucket zone and force dispersal well contrast with that of glimmer and other more parallelized models. Pipelined ADCs are generally utilized in the territories of remote interchanges, advanced endorser line simple front closures, CCD imaging digitizers, studio cameras, ultrasound screens, and numerous other rapid applications.

(2)

2 2. REVIEW OF WORK

The main recorded case of an ADC was a 5-piece, electro-optical and mechanical blaze type converter licensed by Paul Rainey in 1921, used to transmit copy over message lines with 5-piece heartbeat coded tweak (PCM) .The primary all electrical usage came in 1937 by Alec Harvey Reeves, this additionally had a 5-piece goals.

Following the advancement of the transistor in 1947 and the coordinated circuit in 1958, the ADC improvement proceeded in the1960's with for instance a 8-piece, 10 MS/s converter that was utilized in misile-guard programs in the United States.

First business converter, 1954 "DATRAC" 11-Bit, 50-kSPSSAR ADC Designed by Bernard M. Gordon at EPSCO.

In the ongoing years there has been a pattern in ADC research to utilize low precision simple parts which are made up for using computerized blunder adjustment .Because of their ubiquity, pipeline ADCs are accessible in a wide assortment of goals, examining rates, information and yield choices, bundle styles, and expenses. Numerous Pipeline ADCs now offer on-chip input multiplexers, settling on them the perfect decision for multichannel information obtaining framework. A case of present day charge redistribution progressive estimation ADCs is Analog Devices' PulSAR® arrangement. The AD7641 is a 18-piece, 2- MSPS, completely differential, ADC that works from a solitary 2.5 V power flexibly.

The part contains a fast 18-piece testing ADC, an inward change clock, blunder revision circuits, inside reference, and both sequential and equal framework interface ports. The AD7641 is equipment manufacturing plant aligned and extensively tried to guarantee such air conditioning boundaries as sign to- commotion proportion (SNR) and complete consonant contortion (THD), notwithstanding the more customary dc boundaries of addition, counterbalance, and linearity.

3. PIPELINE ADC DESIGN

Figure 1. Shows the square outline of pipeline ADC, All of the pipeline stages are indistinguishable in engineering, yet inspecting capacitances are downsized along stages. Pipeline simple to-computerized converters utilize a procedure like advanced circuit pipelining to exchange inactivity for throughput. In a pipeline converter just a couple of bits are settled at once. This methodology expands the throughput and diminishes the necessary number of comparators contrasted with a glimmer or half-streak converter.

Figure 1. Pipeline ADC

(3)

3

A pipeline ADC (also called subranging quantizer) uses two or more steps of subranging. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC). This difference is then converted finer, and the results are combined in a last step. This can be considered a refinement of the successive-approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit.

The pipeline ADC is an N-step converter, with 1 bit being converted per stage. Able to achieve high resolution (10-13 bits) at relatively fast speeds, the pipeline ADC consists of N stages connected in series (Figure.1).

The Pipelined ADC can be thought of as an amplitude- interleaved topology where errors from one stage are correlated with errors from previous stage. The basic block diagram implementation of an N-bit Pipelined ADC using the cyclic stages is as shown in Figure 2.

Instead of cycling the analog output of the 1 bit/stage section back to its input, we feed the output into next stage. The stages are clocked with opposite phases of the master clock signal. The comparator outputs are labeled digital in figure.

Figure 2 Pipeline ADC based on cyclic stages

The digital comparator outputs are delayed through latches so that the final digital output word corresponds to the input signal sampled N clock cycles earlier. The first stage in figure must be N-bit accurate. It must amplify its analog output voltage, VN-1 to within 1 LSB of the ideal value. The second stage output, VN-2 must be an analog voltage within 2 LSB of its ideal value. The third stage output, VN-3 must be an analog voltage within 4 LSB of its ideal value.

4. CIRCUIT IMPLEMENTATION

A mathematical model of a 4-bit pipeline ADC is presented in this paper. This segment fundamentally centers around the structure and usage of the standard circuit of pipeline ADC, for example, S/H, Comparator and Residue enhancer, and advances explicit circuits as needs be.

5. PIPELINE ADC VERSUS OTHER ADCS

Force dissemination of Pipeline ADCs shifts with the examining rate not at all like Flash and SAR structures. Consequently discover applications in PDAs.

(4)

4

The principle favorable circumstances of SAR ADC's are low force utilization, high goals, and precision. In a SAR ADC, expanded goals accompany the expanded expense of increasingly precise inside parts.

Streak ADC is a lot quicker, less exact and takes more silicon territory because of the quantity of comparators 2N for N bit goals.

Oversampled/Σ-J ADCs have low transformation rates, high exactness, averaging commotion and no prerequisite for cutting or alignment even up to 16 bits of goals.

Types of ADCs

A survey of the field of current A/D converter research reveals that a majority of effort has been directed to four different types of architecture : Pipeline, Flash type, Successive-approximation and oversampled ADC. Each has benefits that are unique to that architecture and span the spectrum of high speed and resolution.

5.1 Successive-approximation ADCs

The method of addressing the digital ramp ADC's shortcomings is the so-called successive approximation ADC. The only change in this design is a very special counter circuit known as a successive-approximation register. Successive approximation converter performs basically a binary search through all possible quantization levels before converging on the final digital answer. The block diagram is shown in figure 3.

Figure 3. Block diagram of SAR ADC

An N-bit register controls the timing of the conversion where N is the resolution of the ADC. VIN is sampled and compared to the output of the DAC. The comparator output controls the direction of the binary search and the output of the successive approximation register (SAR) is the actual digital conversion.

5.2 Direct-conversion ADCs

Blaze or equal converters have the most noteworthy speed of an ADC. As appeared in figure 4 Flash ADC utilizes one comparator per quantization level (2N - 1) and 2N resistors. The reference voltage is separated into 2N values, every one of which is taken care of into comparator. The info voltage is contrasted and each reference worth and results in a thermometer code at the yield of the comparators. A thermometer code displays every one of the zeros for every resistor level if the estimation of VIN is not exactly the incentive on the resistor string, and ones if VIN more noteworthy than or equivalent to voltage on the resistor string. A basic 2N - 1:

(5)

5

N computerized thermometer decoder circuit changes over the analyzed information into a N-bit advanced word.

Figure 4. Block diagram of Flash ADC

The advantage of this converter is the speed with which one conversion can take place. The disadvantage of the Flash ADC is the area and power requirements of the 2N -1 comparators. The speed is limited by the switching of the comparators and the digital logic.

5.3 Sigma-delta ADCs

The oversampling ADC can accomplish a lot higher goals than the Nyquist rate converters. This is on the grounds that computerized signal handling methods are utilized instead of perplexing and exact simple segments. The exactness of this converter doesn't rely upon the segment coordinating, exact example and hold hardware or cutting and just a limited quantity of simple hardware is required. The square outline of Sigma-delta ADC is appeared in figure 5.

Figure 5. Block diagram of Sigma-delta ADC

From the info signal, the yield sign of the 1-piece D/A converter is deducted. The distinction of these two signs is separated by the circle channel and the yield sign of the circle channel is applied to the 1-piece quantizer or A/D converter. The clock recurrence of the framework is high contrasted with the most extreme simple info recurrence. Commotion forming channels can be recalculated into sigma-delta channels demonstrating almost indistinguishable execution. Along these lines an indistinguishable investigation can be performed. The yield of the 1-piece A/D converter is normally applied to a computerized low-pass which rejects flags over

(6)

6

the sign band of intrigue. At that point sub-examining or obliteration is applied to acquire multi-bit yield code. The entire activity brings about a twofold weighted computerized yield signal that can have a base testing proportion equivalent to double the sign data transmission.

6. SIMULATION RESULT

The structured pipeline ADC utilizing the changed blaze ADC topology and the pipeline ADC utilizing the full glimmer ADC approach have been both executed and mimicked in scoundrel Analog Environment, and examination of their exhibition has been made. Figure presents the plots of move bend of nonideal ADC and differential nonlinearity (DNL) and vital nonlinearity (INL) quantization blunders of the planned pipeline ADC. From this examination, we can close the upsides of the pipeline ADC utilizing an adjusted glimmer ADC engineering, which incorporate less parts subsequently littler size, and lower power utilization. These qualities improve this new gadget contender for some applications where force and size are the central point.

7. CONCLUSION

This paper considered the structure of 4 piece Pipeline ADC in < 0.18 µm CMOS innovation. Pipeline ADC is the key plan Block in current microelectronics advanced correspondence framework. With the quick headway of CMOS manufacture innovation and proceeded with expansion of blended simple and advanced VLSI frameworks, the requirement for little measured, low-force and fast simple to-computerized converters has expanded. Along these lines the Pipeline ADC design is mainstream in CMOS innovation. A high goals at a high examining recurrence is conceivable utilizing the pipeline engineering. Sharing of enhancer in a Pipeline converter is conceivable. This lessens power utilization and decreases pass on size.

REFERENCES

1. Y.T. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D Converter,” IEEE J. Solid-State Circuits, vol.35, no.3, pp.308–317, March 2000.

2. S.S. Kim and M.K. Song, “An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver,” Proc. IEEE Int. Symp. Circuits and Systems, vol.1, pp.528–531, May 2001.

3. J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert, and G.Gielen, “A 8-bit 200MS/s interpolating/averaging CMOS A/D converter,” Proc. IEEE Custom Integrated Circuits Conf., pp.445–448, May 2002.

4. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999.

5. T. Stockstad and H. Yoshizawa, "A 0.9-V 0.5 mA Rail-to-Rail CMOS Operational Amplifier,"

IEEE Journal of Solid-State Circuits, vol. 37, pp. 286-292,2002.474

6. Circuit Design Techniques for low-voltage high-speed A/D converters, by Mikko Waltari;

Distributed by Helsinki University of Technology, 2002.

7. Siddharth Devarajan and Larry Singer, “A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC”, IEEE J. Solid-State Circuits, vol. 44, No.12, pp. 3305-3313, Dec. 2009

8. Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” IEEE J.Solid-State Circuits, vol. 39, No. 12, pp. 2139–2151, Dec. 2004.

9. Dwight U. Thomson and Bruce A. Wooley, “A 15-b pipelined CMOS floating point A/D converter, ” Journal of IEEE Solid State Circuit,vol. 36, no. 2, February 2001.

10. R. Samer and Jan Van der Speigel and K. Nagaraj, “Background digital error correction technique for pipeline ADC, “IEEE, 2001.

11. S H Lewis, P. H. Gray “A pipelined 5-Msampled/s 9-bit Analog-to digital converter.", JSSC, December 1987.

12. Van De Plassche, Rudy; Integrated Analog-to-Digital and Digital-to-Analog Converters; Kluwer Academic Publishers, 1994.

13. Baker, R. Jacob, Li, Harry W., Boyce, David E., CMOS Circuit Design, Layout, and Simulation, 1st Edition (IEEE Press Series on Microelectronic Systems).