A Dynamic Latched Comparator for Low Supply Voltages Down to 0.45 V in 65-nm CMOS
Yu Lin1, Kostas Doris2, Hans Hegt1, Arthur van Roermund1
1 Mixed-signal Microelectronics Group, Eindhoven University of Technology, The Netherlands
2 NXP Semiconductors, Eindhoven, The Netherlands [email protected]
Abstract—This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross- coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range. This comparator is designed in 65-nm CMOS technology with standard threshold transistors (VT≈0.4V). Simulation shows that it achieves 5mV sensitivity for a sampling rate of 5GS/s with 1.2V supply voltage, 10mV for 250MS/s with 0.5V supply voltage and 100MS/s with 0.45V supply voltage. The simulated delay time of the proposed comparator is about 30% shorter than the dual-tail dynamic comparator with 0.5V supply voltage and only one third compared to that of the conventional one with 0.6V supply voltage when they are designed to have a similar input referred offset voltage in 65nm CMOS technology.
I. INTRODUCTION
The comparator is a key building block for applications where digital information needs to be recovered from analog signals, such as analog-to-digital (A/D) converters, I/O data receivers, memory bit line detectors, etc. The trend of achieving both higher speed and lower power consumption in these applications makes dynamic latch comparators very attractive, as they achieve fast decisions by strong positive feedback [1] and no static power consumption. Fig. 1(a) shows the conventional dynamic latch comparator, which is commonly referred to as StrongARM latch [2]. It consists of an input differential pair and two cross-coupled nMOS and pMOS pairs which are stacked on top of each other. It achieves a fast decision due to strong positive feedback enabled by two cross-coupled pairs, and a low input referred offset enabled by the input differential pair stage. However, the stacking of transistors in this comparator requires quite a large voltage headroom, which becomes problematic with the supply voltage scaling in advanced CMOS technologies.
Furthermore, since the input pair is stacked with the pMOS and nMOS cross-coupled pairs, the current flowing through these cross-couple pairs is limited by the input common-mode voltage of the differential pair, hence the speed and offset of such a circuit are greatly dependent on its input common- mode voltage, which is a problem for applications requiring a
wide common-mode range, for example A/D converters [3].
In the previous work [4], a dynamic latch comparator with a separated input and cross-coupled stages was introduced to mitigate this drawback, shown in Fig. 1(b). This separation allows the offset and speed of the comparator to be optimatized independently, and allows it to operate at a lower supply voltage as well [4]. However, the stacking of two cross-coupled nMOS and pMOS pairs in this comparator still requires quite a large voltage headroom to accommodate two threshold voltages (VT) plus two overdrive voltage (Vds.sat) to work in saturation. This limits the achievable speed of the comparator at low supply voltage or it may simply fail to work at very low supply voltage.
In this paper, we propose a dynamic latch comparator with a separated input stage and two cross-coupled pair (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as the previous works, as shown in Fig.2. This circuit topology makes it suitable to work at very low supply voltage and achieve faster speed compared to the conventional
This work is sponsored by the Technology Foundation STW, the Netherlands
clk
clk clk
vin M1 M1’ vip
M2 M2’
M3 M3’
S0 S1
S3
S2
S4 Vout Vout’
Vi Vi’
clk
vin M1 M1’ vip
M2 M2’
M3 M3’
S0
Vout Vout’
S1 S2
S3
clk
Vi Vi’
M12 M12’
clk
(b) (a)
Figure 1. (a) conventional dynamic comparator (b) dual-tail dynamic comparator
978-1-4673-0219-7/12/$31.00 ©2012 IEEE 2737
dynamic comparators at low supply voltage. And it is a fully dynamic circuit without any static power consumption.
This paper is organized as following. Section II of this paper describes the comparator circuit and its operation, and then detail circuit analysis and design considerations.
Simulation results are presented in Section III. Section V concludes this paper.
II. PROPOSED COMPARATOR AND COMPARASON WITH PREVIOUS WORKS
A. Circuit Description and Operation
The schematic of the proposed dynamic comparator is shown in Fig. 2 and its linear time variant model is shown in Fig. 3. The proposed comparator consists of an input differential pair stage, two latch stages in parallel namely main stage and auxiliary stage, and some reset switches. Each of the latch stages consists of a cross-coupled pair and two input differential pairs. One of the input differential pair (M12/M12’
or M13/M13’) of the latch stage passes the input signal for comparison, while the other one (M32/M32’ or M23’/M23) is controlled by the output of the other latch stage which forms another positive feedback loop besides the cross-coupled pairs during regeneration.
The comparator operates similar to the conventional dynamic comparators (shown in Fig. 1). It goes through a set of operating phases each cycle, namely: resetting, sampling, regeneration, and decision phases as shown in Fig. 4.
The comparator shown in Fig.2 is in the resetting phase when the clock input clk is low. The output nodes Vout/Vout’
and internal nodes Vi/Vi’ are precharged to supply voltage by switches S1-S2, while nodes Vaux/Vaux’ are discharged to ground, as it is shown in Fig. 4. And switches S0 and S3-S4 are off to prevent static current consumption in this phase.
The sampling phase starts when clk is switched to high.
S1-S2 are turned off, the input differential pair M1 and M1’
discharges the nodes Vi and Vi’ at a rate depending on the input signal difference (Vin- Vin’), hence an input dependent
differential voltage ∆vi is built up at the output of the input differential pair stage. The intermediate stages formed by M12 and M13 then pass this voltage difference to the nodes Vaux/Vaux’ and Vout/Vout’ in both the auxiliary and main latch stages to be used as an initial voltage for regeneration.
During this phase, both the cross-coupled pairs in the main stage (nMOS) and the auxiliary stage (pMOS) are turned on.
The regeneration phase begins when the intermediate stages (M12/M12’and M13/M13’) loose the strength to clamp the outputs to the same voltage levels (shown in Fig. 4). And an initial voltage difference built up at the outputs during the sampling phase causes both the cross-coupled pairs to leave the unstable equilibrium state. Both the cross-coupled pairs (M2/M2’and M3/M3’) regenerate the voltage difference stored on the output nodes via positive feedback in a parallel fashion. Their output are then coupled by two cascade gm
stages (M23/M23’ or M32’/M32) which forms another positive feedback loop to further enhance the regeneration speed, as will be detailed in the following analysis.
B. small signal analysis and design considerations
The small signal model of the comparator in the sampling phase is shown in Fig. 5 (a). From this small signal model, we Figure 4. Signal waveform of the proposed comparator
gm1/C
gm12 +++ 1/Cout
gm2 gm13 +++ 1/Caux
gm32
gm23 gm3
Auxiliary stage
∫
reset
∫
reset
∫
reset
Vin
Vout Main stage
Input stage
Vaux
Vi
Figure 3. Linear time variant model of the proposed comparator
M2 M2’
M32 M32’
Vout Vout’
Vi’
Vi
M12 M12’
M23 M23’
M3 M3’
Vaux
M13 M13’
clk
Vin M1 M1’ Vin’
S0
S1 clk S2
S4 clk
Vaux’
clk S3
Input differential pair (stage 1)
Main latch (stage 2) Auxiliary latch (stage 3)
Figure 2. Schematic of the proposed dynamic latch comparator
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can derive the transfer function assuming the sampling phase lasts until t0, which are given by
0 12
1 0
12 0
0 1
0 1 0
0 0
) 1 (
) 1 (
t C vin
C g dt g
vi C g
t vo
t C vin dt g vin C g
t vi
out i
m m t
m out
i m t
m i
(1)(2) where ∆vin is equal to Vin-Vin’, and ∆vi(t) and ∆vo(t) are equal to Vi-Vi’ and Vout-Vout’, gm1 and gm12 are the transconductances of M1/M1’ and M12/M12’, and Ci and Cout are capacitance at nodes Vi and Vout. Note that the resulting transfer function corresponds to two cascaded integrations.
The regeneration process can be approximately analyzed using a small signal model as shown in Fig. 5 (b). In this equivalent circuit, gm2, gm3, gm23 and gm32 are the transconductances of M2/M2’, M3/M3’, M23/M23’ and M32/M32’ respectively. From this small signal model, using the KCL for the output nodes we can derive the following coupled first order differential equations:
) ( ' )
( ) '
(
) ( ' )
( ) '
(
23 3
32 2
t Vout g t Vaux dt g
t dVaux C
t Vaux g t Vout dt g
t dVout C
m m
aux
m m
out (3)
) ( ' )
(
) ( ' )
(
t Vout t
Vout
t Vaux t
Vaux (4)
Solving (3) and (4) together with the initial condition:
2 / ) ( ) 0 ( ) 0
( Vout vot0
Vaux (5)
and assuming gm2=gm3, gm23 = gm32 and Cout=Caux for simplicity to understand the behavior of the circuit, we obtain the differential output voltage:
) exp(
) ( )
( 0 2 32 t
C g t g
vo t Vout
out m
m
(6)
From (1) and (2), in the sampling phase, as t0 is proportional to the capacitors (Ci and Cout) over their discharging current (Id), therefore it is important to maximize the transconductance over discharging current (gm1/Id1 and gm12/Id2) in order to minimize the offset and noise contributions from the latch stages [5-7].
While in the regeneration phase, the regeneration speed depends on the transconductance of M2 and M32 and the output loading capacitance, shown in (6). The loading capacitance Cout is the sum of the external load Cext and a parasitic component Clat. As gm is proportional to
W / L V
gt, where W and L are the width and length of the transistor and Vgt is the effective gate-source overdrive voltage. And Clat is proportional to W L
which is the parasitic capacitance at the output of the latch (mainly contributed by M2 and M23).By maximizing Vgt at the initial step of regeneration phase, using minimum transistor length and taking into account Cext
to optimized the width of the transistors, faster regeneration
speed can be achieved [8].
C. Comparison with previous works
The separation of the input stage and the cross-coupled pair stages keeps the same advantage as the dual-tail comparator [4]. It allows a large current in the latch stage for fast latching independent of the input common mode voltage and a small current in the input stage for low offset and low noise compared to the conventional. And the intermediate stage provides additional shielding between the input and output of the comparator which results in less kickback noise.
The further separation of the cross-coupled nMOS and pMOS pairs stages allows the latch stages to work at a lower supply voltage. The minimum supply voltage now required to assure the transistors in the latch stages to work in saturation is only one VT plus two Vds.sat. Therefore, the supply voltage required for the proposed comparator is at least one VT lower than the previous works shown in Fig. 1 . The separation of the input and latch stages may result in extra power consumption as more nodes need to be charged and discharged, but it enables the comparator to operate at a much lower supply voltage.
Furthermore, when clk goes high, both the cross-coupled pairs of the proposed comparator become active at the same time with a large Vgt equals to Vdd-VT, while for the comparators shown in Fig. 1, they become active in a series fashion. In the conventional dynamic comparator, the nMOS pair turns on first while the pMOS pair becomes active only after Vout/Vout’ drop below Vdd-VT, and the dual-tail comparator is the other way around. Therefore the effective total transconductance at the initial step of the regeneration phase is only half of that of the proposed comparator. A larger effective transconductance allows a faster regeneration speed and hence shorter delay time.
gm3Vaux’ gm23Vout’
Vaux
gm3Vaux
Caux Caux
Vaux’
gm23Vout gm2Vout’ gm32Vaux’
Vout
gm2Vout
Cout Cout
Vout’
gm32Vaux
(b)
Vin gm1Vin gm12Vi
Vi Vout
(a)
Cout
Ci
Figure 5. Small signal models for the comparator in (a) sampling phase and (b) regeneration phase
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III. SIMULATION
The proposed comparator is designed in TSMC CMOS 65nm technology. Its performance is simulated and compared with the other dynamic comparators shown in Fig.1 (a) and (b) which are also designed in the same technology. For a fair comparison, all three comparators are designed to have a similar input referred offset voltage, and with the same external loading capacitance Cext (~5fF).
Fig. 6 shows the simulated delay time (ns) of each comparator versus the supply voltages with an input voltage different of 50mV. The delay time is defined as the time the output difference takes to reach ½Vdd . The delay time is a suitable quantity in characterizing the comparator’s speed of operation [8], a shorter delay time means a faster comparison speed. In Fig. 6, it is shown that the delay time of the proposed comparator is about 30% shorter than the dual-tail comparator with 0.5V supply voltage and it is only one third compared to that of the conventional comparator with 0.6V supply voltage.
Fig. 7-8 show the output waveforms of the proposed comparator for a sampling rate of 5GS/s and 5mV input difference at 1.2V supply voltage, 250MS/s and 10mV input difference at 0.5V. In Fig. 9, it also shows that the proposed comparator is able to work at a supply voltage of only 0.45V with a sampling rate of 100MS/s and 10mV input difference.
IV. CONCLUSION
A dynamic latch comparator suitable for very low supply voltage applications is presented in this paper. Analysis and simulation show that it is able works at very lower supply voltage and with faster speed compared to the previous works (dual-tail and conventional dynamic comparators). Moreover, it is a fully dynamic circuit without any static power consumption.
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[8] G. M. Yin, F. O. Eynde, and W. Sansen, "A high-speed comparator with 8-bit resolution", IEEE J. Solid-State Circuits, vol. 27, pp.208 -
211 1992 Figure 9. Output waveform (∆vin = 10mV,Vdd=0.45V clk=100M)
Figure 8. Output waveform (∆vin =10mV,Vdd=0.5V clk=200M) Figure 7. Output waveform (∆vin = 5mV,Vdd=1.2V clk=5G) Figure 6. Delay time versus supply voltage (∆vin=50mV,
Vcm=Vdd-0.1V)
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