A Sub-1V High-Gain Two-Stage OTA Using Bulk-Driven and Positive Feedback Techniques

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Abstract—This paper presents the design and simulation of a fully differential two-stage operational trans-conductance amplifier (OTA) in a 0.18μm CMOS process with a 0.9V supply voltage. For this purpose, both the bulk-driven and positive feedback techniques are employed. These techniques increase the dc gain about 18.4 dB without any change in the power dissipation, unity-gain bandwidth, phase margin, and other specifications of the OTA. The simulation results show a dc gain of 73.8dB, unity-gain bandwidth of 272MHz and phase margin of 64°. The slew rate is 190V/μs and the OTA dissipates about 2.72mW from a 0.9V supply voltage.

Index Terms—Bulk-driven, Operational transconductance amplifier(OTA), Positive feedback

I. INTRODUCTION

eduction in dimensions and gate oxide thickness of modern MOS transistors, forces supply voltages to decrease in order to have highly reliable circuits. On the other hand, in modern CMOS technologies, the threshold voltage does not decrease proportional to the supply voltage This problem has faced the analog designers with new challenges[1]. Operational amplifiers are known as one of the most essential parts of analog circuits. Designing a high dc gain, high bandwidth, and high swing CMOS OTA in a low supply voltage is very complicated. Compared to single-stage amplifiers, two stage amplifiers have higher dc gain and swing but because of their extra poles and zeros, if they do not compensate properly, they can easily be unstable[2],[3]. In this paper, both the bulk-driven and positive feedback methods[4],[5] are used for increasing the dc gain of the OTA of Fig. 1 without any change in the bandwidth or power consumption. The proposed OTA is described in section 2.

The frequency response of the proposed OTA is investigated in section 3. The simulation results are summarized in section 4 and finally the paper is concluded in section 5.

Manuscript received May 16, 2010.

H. Khameh is with Department of Electrical and Computer Engineering, Islamic Azad University-Qazvin branch, Qazvin, Iran (e-mail:

[email protected]).

H. Shamsi is with Department of Electrical and Computer Engineering, K.N. Toosi University of Technology, Tehran, Iran (e-mail:

[email protected]).

Fig.1. A Conventional two stage OTA

II. PROPOSED OTA

In order to have a high-gain, and large-swing OTA with 0.9V supply voltage, a two-stage class A OTA structure is chosen. A single-stage cascode topology would not be appropriate for designing a large-swing, high-gain amplifier under low-voltage operation. Instead, a two-stage topology, as illustrated in Fig. 1 is often adopted to attain both the desired gain and output swing. For a two-stage amplifier, the second stage is designed to enable a large output swing while the first stage contributes to the total gain. The two-stage amplifier is stabilized by the compensation capacitors. A left-half-plane zero can be added to the amplifier by connecting a resistor in series with the capacitor to improve the frequency response [2],[3]. The main bottleneck of our design is that we want to design a high performance OTA with a 0.9V supply voltage in a standard 0.18μm, 1.8V CMOS technology. The arising question is: "why 0.9V?". The response is as follows: Since the low-voltage technologies such as 90nm, 65nm, 45nm CMOS technologies are more expensive than their older counterparts are, so it is economical to design the low-voltage circuits with older CMOS technologies. However, this approach is very complicated. For example, the threshold voltage of transistors in a 0.18μm CMOS technology is about 0.5V while the threshold voltage in a 90nm CMOS technology is about 0.2V.

A Sub-1V High-Gain Two-Stage OTA Using Bulk-Driven and Positive Feedback Techniques

H. Khameh and H. Shamsi, Member, IEEE

R

5th European Conference on Circuits and Systems for Communications (ECCSC'10), November 23–25, 2010, Belgrade, Serbia

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Fig. 2.Proposed OTA

The proposed OTA is shown in Fig.2 where by applying the output signal Vout- to the bulk terminal of M₇, a positive feedback is created. The Positive feedback can create right half-plane poles and make the circuit unstable. Therefore, for controlling the gain of the feedback loop and avoiding the instability, two resistors (R1, R2) are used as the voltage divider. The division factor of the voltage divider, K, is shown in equation (1). The value of (R₁, R₂) is chosen much bigger than drain-source resistor of transistors (r_ds).

2 1

2

R R K R

(1) The differential dc gain of the OTA, A_dc, is obtained as shown in equation (2) where g_m1 and g_m7 denote the transconductance of transistors M₁ and M₇, respectively.

Moreover, R_A and R_B are the output resistance of the first and second stages. The equations of R_A and R_B are shown in (3) and (4) where r_ds represents the drain-source resistor of the related transistors. In addition, g_mb7 is the transconductance of the bulk-driven transistor M₇ that represents the body effect of the transistor.

7 1

1

7

m B

dc m A

mb B

A g R g R

g R K

(2)

3 1 ds ds

A

r r

R

(3)

7 5 ds ds

B

r r

R

(4)

5)

IV. Frequency Response

Frequency response of the conventional two-stage OTA Fig.1 using Miller compensation is investigated in [2].

According to the analyses of [2], the transfer function of the OTA is equal to:

) 1 )(

1 (

) 1 ( )

(

2 1

1

p p

z dc

s s

A s s

A

Z Z

Z

(5)

where A_dc, represents the dc gain of the OTA as shown in equation (6). Besides, poles and zero is obtained as shown bellow[2].

B m A m

dc

g R g R

A

₁ ₇ (6)

A C B m

p¹

g

₇

R C R

Z 1

(7)

) (

7 2

L A

m

P

C C

g

Z

(8)

C m

z

C

g

₇

Z

(9)

3 4

( )

L B B

R R R R #R

2

1 7 B eq

mb B

R R

g R K

Fig 3. Small-signal model of the Proposed OTA

In the proposed structure, applying the positive feedback changes the frequency response of the circuit. In the small signal model of the OTA Fig.3, the positive feedback signal, applied to the bulk terminal of M7, is modeled by a voltage- controlled current-source (VCCS). The current of this VCCS is equal to: I g_mb₇KV_out. Since the drain voltage of M7 is V_out, so it is easily understood that this VCCS behaves as a negative resistor R ( g_mb₇K)¹, paralleled with the load resistor R_L #R_B. Therefore, the equivalent output conductance G_eq₂ is obtained as shown in equation (10). Thus, equation (6) is modified as follows:

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K g R G

G

_B _mb

eq

eq 7

1

(10)

K g G R g g R g R g A

mb B

m A m eq m A m dc

7 7 1

7

1

(11)

K R g

R R g

g R g R g A

B mb

B m A m eq m A m dc

7 7 1

7

1

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This equation is identical to the equation of (2). If we consider the formulas of zero and poles described in relations (7) to (9) [2], it will be understood that only the first pole Z_p₁ of the conventional OTA depends on R_B. Therefore, the positive feedback does not change the other poles and zeros. It only changes the location of the first pole. In equation (7), by Substituting R_eq₂ instead of

R

_B, the new first pole is obtained as follows:

A C B m

B mb

p

g R C R

K R g

7 7 1

1

Z

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Assuming

1 g

_mb₇

R

_B

K | 0 . 1

, it is understood that using both the bulk-driven and positive feedback techniques causes the dc gain to increase about ten times and the first pole to decrease about one-decade proportional to 1g_mb7R_BK^, while other poles and zeros stay constant. In other words, we have performed the pole splitting without any decrease in the unity-gain bandwidth of the OTA (UGBW A_dcuZ_p₁). Note that if 1g_mb₇R K_B <0, we will have a right half-plane pole and the OTA will becom unstable.

V. SIMULATION RESULTS

Both the conventional and proposed OTAs, shown in Fig. 1 and Fig. 2 respectively, are designed and simulated with HSPICE in a 0.18m CMOS technology. The supply voltage of OTAs is 0.9V. The size of transistors and values of other circuit elements are summarized in Table I, The Frequency responses of both conventional and proposed OTA are shown in Fig 4 and 5 Simulation results show that the dc gain of the proposed OTA is 73.8dB, 18.4 dB greater than that of the conventional OTA. Unity-gain bandwidth and phase margin are 272 MHz and 64°, respectively. The slew rate is 190V/s and the OTA dissipates about 1.42mW from a 0.9V supply voltage. In Table II, the specifications of both conventional and proposed OTAs are summarized. It is observed that excluding the dc gain, the proposed method does not change the unity-gain frequency, phase margin, power consumption, noise and other specifications of the conventional OTA. As an advantage, it provides 18.4dB DC gain improvement.

TABLE.I SIZE OF TRANSISTORS

Parameter Value Parameter Value (W/L)1,2 4×60m/0.36 m R1 , R3 500k (W/L)_3,4 2×30m/0.36 m R2 , R4 50 k (W/L)_5,6 2×80m/0.36m CL 2pF (W/L)_7,8 2×30m/0.36m C_c 1.7pF (W/L)9 2×90m/0.18 m RC 0.25 k

Fig. 4. Gain of the proposed and Conventional two-stage OTA

Fig.5. Comparing gain phase of the proposed and Conventional two-stage OTA

TABLE.II SIMULATION RESULTS SUMMARY Parameter Conventional

structre

Proposed Structure

Supply voltage 0.9V 0.9V

Technology 0.18m 0.18m

DC Gain 55.4dB 73.8dB

UGBW 282MHz 272MHz

Phase Margin 60° 64°

Slew Rate 190V/ s 190V/s

Input-referred noise@100KHz

34 nV/ Hz _33.8nV Hz

Power Dissipation 1.42mW 1.42mW

Output swing Vpp 1v 1.1 v

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VI. CONCLUSIONS

In this paper a 0.9V two stage OTA is designed. Using both the bulk-driven and positive feedback techniques,the DCgain of this OTA is increased about 18.5dB without consuming more power and changing other specifications.

REFERENCES

[1] B. J. Blalock, P. E. Allen, G. A. Rincon-Mora, “Designing 1-V OP Amps Using Standard Digital CMOS Technology,” IEEE Transations on Circuit and Systems: Analog and Digital Signal Processing, vol.45, No.45,pp.769-780, Jul.1998.

[2] D. Johns and K. Martin, Analog Integrated Circuit Design, NewYork: Wiley,1997, ch. 5.

[3] B. Razavi, Design of Analog CMOS Integrated Circuits, New York:

McGraw-Hill, 2001.

[4] M. Asloni, K. Hadidi, A. Khohei, “Design of a New Folded Cascode Op-Amp Using Positive Feedback and Bulk Aplification” IEICE Transactions, 90-C(6):1253-125, Jun 2007.

[5] M. Trakimas, S. Sonkusale, “ A 0.5V Bulk- Input Operational Transconductance Amplifier with Improved Common-Mode Feedback,”

IEEE Symposium on Circuits and systems, pp.2224-2227, May 2007.

[6] S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5V Analog circuit Techniques and Their Application in OTA and Filter Design,” IEEE J.

Solid-state Circuits, Vol. 40, no. 12, pp. 2373-2387, Dec. 2005.

[7] Y. Haga, H. Zare- Hoseini, L. Berkovi, and I. Kale, “Design of a 0.8volt Fully differential CMOS OTA Using the Bulk-Drive Technique,” in proc. IEEE Intl .Symp.circuit& Systems, pp. 220- 223 Systems, pp. 220 223. May 2005.

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