International Conference on Electrical Engineering and Computer Science ICEECS 2015
Design and Implementation of a New Soft Switching Interleaved Boost Converter with Low Losses
1Ehsan Shahri, 2Majid Dehghani
1,2 Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran Email: 1 [email protected], 2[email protected]
Abstract: This paper proposed a new soft switching interleave boost converter with high voltage gain. In this converter two switches operate under ZVS condition without adding any auxiliary switches. The flyback converters which connected to the output in series lead to high voltage gain and less voltage stress on the power devices. In this paper simulation and experimental results verify theoretical analysis.
Index terms: Interleaved boost converter, ZVS, High voltage gain, Soft Switching, PWM
I. INTRODUCTION
High step-up DC/DC converters have many industry applications, such as the front-end stage for a battery source, UPS and solar energy sources, etc.
Theoretically, conventional boost converters are able to achieve high step-up voltage gain in heavy duty load conditions. However, the voltage gain of the boost converter is limited to the losses associated with the inductor, filter capacitor, main power switch and rectifier diode [1-3]. Several soft-switching techniques for providing zero-voltage switching (ZVS) or zero-current switching (ZCS) condition have been proposed to substantially reduce switching losses, and hence, attain high efficiency at increased frequencies. There are many resonant or quasi resonant converters with the advantages of ZVS or ZCS introduced in [4-6]. The main problem with these kinds of converters is the high voltage stresses on the power switches, especially for the high – input voltage ones. Passive snubbers for providing ZVS are attractive [7-9], because they have no extra active switches and therefore, feature a simpler control scheme and lower cost. However, the circuit topology is complicated and not easy to analyze. Auxiliary active snubbers are also developed to reduce switching losses [10-13]. These snubbers have additional auxiliary switch and gated in complimentary with the main switch. But this auxiliary circuit cause high current stress in the main switches and this converter has lost duty cycle.
This paper proposed a new soft switching interleave boost converter with high voltage gain. In this converter two switches operate under ZVS condition without adding any auxiliary switches.
Since this converter have two fly-back transformers, the voltage gain of converter increases. In this paper simulation and experimental results are presented to verify theoretical analysis. The circuit configuration and principle of operation of the proposed converter
is illustrated in section 1. In section 2, its steady state analysis and in section 3 design procedure of proposed converter is presented. The obtained simulation results of proposed converter are presented in section 4. Finally In section 5, obtained experimental results of proposed converter are presented. The simulation results and experimental results verify theoretical analysis.
II. Circuit Configuration and Operation Principle of the Proposed Converter 1. Circuit description
The proposed soft switching interleaved boost converter is shown in Fig. 1 where S1 and S2 are the main switches, C1 –C3 are the output capacitors, RO is the load resistance and Ls is the auxiliary inductor. T1
and T2 are the flyback transformers. Also D1-D4 are the output diodes. CS1 and CS2 are snubber capacitors of switches S1 and S2 respectively. Also DS1 and DS2
are body diodes of switches S1 and S2 respectively.
The switches in this converter controlled by PWM signals therefore implementation of control circuit is very simple.
Figure 1: The schematic of proposed interleaved
Boost converter
2. Converter Operation
In order to simplify the steady state analysis, the following assumptions are made.
a. All parasitic components are neglected.
b. The output capacitors are large enough, so that the output voltage can be considered constant in a switching cycle.
The main waveforms of the proposed converter are given in Fig. 2 the equivalent circuit for each operating mode of the proposed soft switching interleaved boost converter is shown in Fig. 3. First assume that S1 and S2 are on and energy is not transferred to the output.
Figure 2: Main waveforms of the proposed converter
Mode1: When S2 turns off this mode starts. In this mode the magnetizing current of T2 charges CS2
to VC1 linearly and magnetizing inductor of T1 is charged similar to previous mode with Vin/Lm1 slope.
This mode ends when D2 is turned on.
Mode2: This mode begins when D2 and D4
conduct. In this mode the voltage across the LS equal to –VC1 and thus ILS starts to decreases with slope of –
VC1/LS .Also S1 current starts to increase and when this current wants to change direction this mode ends.
) 1 ( t
L I v t i
S C l ls
) 1
( = −
) 2 ( t
L t v i
S C S
1 1( )=
) 3 ( t
L I v t i
S C l D
1 2()=2 −
Mode3: In this mode current transfer from body diode of S1 to S1. Also ILs decrease with the same slope of previous mode. When this current changes direction and it be equal to ILm2, this mode comes to an end. In this instant D2 is turned off and S1 current is equal to ILm1+ILm2. In this mode ILm1 continues increasing.
) 4 ( )
cos(
)
( 1
2 t v t
vds = c ω
) 5 (
l
s C
ls t v wc t I
i ()=− 1 sin(ω )−
Mode4: when D2 is turned off this mode start .In this mode LS discharges CS2 is resonant fashion. This mode end when CS2 discharged completely.
) 6 ( )
sin(
2 ) ( )
( 1
1 t
c v I t v
s L C
ds ω
+ω
=
) 7 ( )
cos(
) 2 (
)
(t I v1 c I t
ils = l− cω s+ l ω
) 8 ( ω
ω )) 2
( sin( 1 1
34
s l C
C v I c
t = v +
Mode5: when CS2 discharged completely and body diode of S2 Condit this mode begins. After this instant, S2 can be turned on under ZVS condition .After S2
turning on, ILM2 start to increasing lineally with slope of Vin/LM2.
Mode6: This mode start when S1 turn off. In this mod ILS start to charge CS1 .when CS1 charges to VC1, D1 and D3 conducts and this mode ends.
III. Analysis of the Proposed Converter 1. Voltage DC gain
By writing Volt-Sec balance for two flyback transformer the following equations are obtained.
1. n
D3
Ro
Vdc D4
+ VC3-
D1
+ Ls -
+ VC2 - + VC1- D2
1.m
DS1
S1
+ VDS1
-
CS1 DS2
S2 +
VDS2 -
CS2
(a)
1. n
D3
Ro
Vdc D4
+ VC3-
D1
+ Ls -
+ VC2 - + VC1- D2
1.m
DS1
S1 +
VDS1 -
CS1 DS2
S2 +
VDS2 -
CS2
(b)
1. n
D3
Ro
Vdc D4
+ VC3-
D1
+ Ls -
+ VC2 - + VC1- D2
1.m
DS1 S1 +
VDS1 -
CS1 DS2
S2 +
VDS2 -
CS2
(c)
1. n
D3
Ro
Vdc D4
+ VC3-
D1
+ Ls -
+ VC2 - + VC1- D2
1.m
DS1 S1 +
VDS1 -
CS1 DS2
S2 +
VDS2 -
CS2
(d)
1. n
D3
Ro
Vdc D4
+ VC3-
D1
+ Ls -
+ VC2 - + VC1- D2
1.m
DS1
S1 +
VDS1 -
CS1 DS2
S2 +
VDS2 -
CS2
(e)
1. n
D3
Ro
Vdc D4
+ VC3-
D1
+ Ls -
+ VC2 - + VC1- D2
1.m
DS1
S1 +
VDS1 -
CS1 DS2
S2 +
VDS2 -
CS2
(f)
Figure 3: Equivalent circuits for each operating interval of the proposed converter:
(a):t0-t1, (b):t1-t2, (c):t2-t3, (d):t3-t4, (e):t4-t5, (f):t5-t6 (The blue colored elements do not conduct current).
) 9 ( )
V V ( T ) D (
DTVin= 1− C1− in
) 10 ( D
VC Vin
= −
1 1
) 11 (
2
1 in C
C V V
V − =
) 12 (
3
1 in C
C V V
V − =
) 13 ( D
V DV VC C in
= −
= 2 1
3
As you can see in Fig. 1 the output voltage is equal to sum of output capacitors thus the voltage gain of proposed converter is calculated.
) 14 (
3
2
1 C C
C
O V V V
V = + +
) 15 ( D
D V Vo
in −
= + 1
1 2
Fig.4 shows the output power (Vo/Vin) of proposed converter against the duty cycle D. As shown the Fig.4 proposed converter gain is boosted against basic interleaved converter.
Figure 4: The output power converter (PO) against the duty cycle (D)
2. Calculating Value of Ls
The current slop of LS inductor according to mode 2 equal (VC/LS) to this :
) 16 ( T
D I L
v in
S C
) 1 (
1
= −
) 17 (
in C
S I
Tv L =(1−D) 1
) 18 (
D
D I I v v
o in in c
−
= +
= 1
1
1 η 2
) 19 ( D
I D Iin o
−
= + 1
1 η 2
) 20 ( )
1 2 ( . .
) 1 ( 1
1 2
) 1
( 1 2 1
+
= −
− +
= −
D I f
v D D
I D Tv L D
O c
O c
S η η
IV. Design Procedure
The proposed interleaved boost converter without auxiliary Switch is designed for the required input and output voltages.
Then, in order to design the proposed converter the following steps should be performed.
Step 1: Calculation of snubber capacitors
The snubber capacitors are designed according to the output power and main switches speed [14].
Step 2: ZVS condition
Inductors Ls provide ZVS condition for switches at the turn on instant. For achieve ZVS condition of main switches S1 and S2, the current of leakage inductance Ls should discharge snubber capacitors CS2 and CS1, respectively. Therefore the relation (7) is obtained. ILS is the converter minimum output current which guarantees zero voltage switching (ZVS) condition for main switches. Using the above relation, switching frequency versus leakage inductance for various output powers can be illustrated as shown in Fig. 5(a).
(a)
(b)
Figure 5: The Relationship between the switching frequency and leakage inductor to several output power (a) and (b) 3D graph.
Step 3: Design of auxiliary inductors
In the relation (20) the assumed value of
η
=1. By using (15) in the above relation, LS can be calculated based of PO. Fig.5(b) shows 3D graph relationship between the switching frequency and leakage inductor to several output power. In which that Vin=24 V.Step 4:Output Power of converter
The ILs value changed to ILM2 In mode3. When D2 is off, S1
will equal to (ILm1+ILm2) and the Ls change the charge of the CS2 to discharge in the next mode, therefore, equation (15) can be rewrite such as follow:
) 23 ( T
D Iin D T
D D Ls Vo
) 1 (
) 1 2 ( )
1 (
ILm2) + ILm1 )(
1 2 (
−
= +
−
= +
With using equations (18), (19) :
) 24 ( Iin
Vin Vin
Iin=η(Io.Vo)→ =η(Io.Vo)
The converter must be keep the stability of (Vo) in constant frequency and certain inductance against of the variation of current of load and the variation of the input voltage (Vin).
now, with using the equation (22), The output power of converter can be calculate as follow :
) 25 ( Ls
f Vc D Po Vin
. .
1 ).
1 .(
η
= −
Step 5: Input current ripple
In Fig. 2 the graph of input transformer's currents (ILm1, ILm2) is shown. The input voltage charged the Fly back transformer with rate Vin/L. therefore, the value of input current ripple of input transformer have a relation with difference of input current when each switch is on and off.
) 26 ( Lm
DTVin ILm= ∆
The Iin is sum of input transformer's currents, therefore:
) 27 ( Lm
TVin D T D Lm DT
Iin=Vin( −(1− ) )=(2 −1) ∆
In equation (DT) is switch ON-time duration and (1-DT) is switch OFF-time duration.
V. Simulation Results
The simulation results are presented in this section to verify the effectiveness of the proposed converter. Fig. 6 and Fig. 7 shows the waveform of drain-source voltage and current of main switches S1 and S2 to illustrate the ZVZC feature.
Figure 6: waveform of drain-source voltage and current (dashed) of main switch S1 (vertical scale 50V/div or 10A/div, time scale 1µs/div)
Figure 7: waveform of drain-source voltage and current (dashed) of main switch S2 (vertical scale 50V/div or 10A/div, time scale 1µs/div)
Fig. 8 shows the current waveforms of Ls. It can be observed that the switches currents are negative before the turn on instant of switching devices. Therefore their body diodes are conducting and switches are turned on under ZVZC. Fig. 9 shows the current waveform of D1 and D2.
Figure 8: The current waveforms of Ls (Vertical 10A/div, time scale 2µs/div)
) 21 ( Vo
I f L Vin
O
S . .
= 2
) 22 ( Po
f LS Vin
.
= 2
Figure 9: The current waveform of D1 and D2 (Vertical scale 10A/div, time scale 1µs/div)
Fig.10 shows waveform of transformer current ILm1 and ILm2. Input current Iin, will equal to (ILm1+ILm2). Waveform of drain-source voltage Vgs and gate-source voltage Vds of main switch S1 shows in Fig.11.
Figure 10: waveform of transformer current (ILm1) and (ILm2-dashed).
(Vertical scale 10A/div, time scale 2µs/div)
Figure 11: waveform of gate-source voltage (Vgs) and drain-source voltage (Vds- dashed) of main switch S1 (vertical scale 50V/div, time scale 2µs/div)
Figure 12: waveform of output current (IO) (Vertical scale 45mA/div)
And Finally, Fig.12 and Fig.13 shows the average of output current and output voltage, which are about 2 (A) and 240 (V) respectively.
Figure 13: waveform of output voltage (VO) (Vertical scale 55V/div)
VI. Experimental results
The In this section, the experimental results of the implemented proposed converter that described in previous sections, are presented. Table 1 shows the specifications of proposed converter. The component list for practical implementation is shown in Table 2.
TABLE I. PROPOSED CONVERTER SPECIFICATIONS
Specifications Value
Switching frequency fs (Hz) 100 KHz Input voltage Vin 24 V Output voltage Vo 240 V
Output power Po 500 W
TABLE II. PROPOSED CONVERTER SPECIFICATIONS
Components Part name/Value
Inductors LS 10μH
Transformer m , n 1
Capacitors C1,C2,C3 220μF
Diodes D1-D4 MUR460
Mosfet S1,S2 IRF150
Fig. 14 (a) and (b) show the drain-source voltage and current of main switches S1 and S2 Respectively, it’s illustrate the ZVS feature at turn on instant and almost ZVS condition at turn off instant. In this figure, the main switches currents are negative before the turn on instant of switching devices, therefore their body diodes are conducting and switches are turned on under ZVZS condition. Part (c) shows the measured waveforms of current of auxiliary inductor LS and (d) shows soft switching conditions and measured waveforms current of D1.
In the proposed converter, snubber capacitors provide ZVS conditions and in the hard switching counterpart, the leakage
inductance energy is absorbed by the output capacitance of main switches and thus main switches voltage stresses are increased to approximately 100 V. Fig. 15 shows the efficiency of the proposed converter versus various output power. Fig 16 shows the laboratory prototype proposed interleaved DC-DC boost converter.
(a)
(b)
(c)
(d)
Figure 14: (a): The voltage (top) and current (bottom) waveforms of main switch S1(vertical scale 35 V/div or 10 A/div - time scale 2.5µs/div and ),
(b): The voltage (top) and current (bottom) waveforms of main switch S2(vertical scale 35 V/div or 10 A/div - time scale 2.5µs/div and ), (c) : The current waveforms of Ls (vertical 10A/div - time scale 2.5µs/div), (d): The
current waveform of D1 (vertical scale 10A/div, time scale 1µs/div).
Figure 15: The efficiency of the proposed converter versus Various output power.
Figure 16: Laboratory prototype Proposed interleaved DC-DC boost converter. (a): flyback transformers, (b): Main switches, (c) Inductor, (d):
Load resistance, (e): Output diodes, (f): Output capacitors.
The proposed converter and converter of Refs. [6]-[8]-[12]
are simulated in PSPICE software and comparison results are illustrated in Table 3. The simulation results show better efficiency compared with Oder Refrens with lower number of additional components in the proposed converter.
TABLE III. COMPARISON BETWEEN THE PROPOSED CONVERTER AND REFERENCED CONVERTERS.(A):NUMBER OF THE AUXILIARY COMPONENT. (B):MAIN SWITCH VOLTAGE STRESS (V).(C):MAIN SWITCH CURRENT STRESS
(A).(D):EFFICIENCY (%)
d c
b a
Compare Parameter
92 24
98 1
Proposed Converter
91 25
206 1
Converter of Ref. [6]
90 25
85 2
Converter of Ref. [8]
90 25
84 4
Converter of Ref. [12]
VII. CONCLUSION
This paper proposed a new soft switching interleave boost converter with high voltage gain and low losses. In this converter two switches operate under ZVS condition without adding any auxiliary switches. Therefore the conduction losses decrease. The flyback converters which connected to the output in series lead to high voltage gain and less voltage stress on the power devices. Therefore this converter can operate under higher switching frequency to further reduce the converter size, weight and electromagnetic interference. This converter controlled by PWM signals so implementation of control circuit is very simple. In this paper simulation and experimental results of proposed converter confirm the integrity of the proposed circuit.
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