A new low-power, universal, multi-mode Gm-C fi lter in CNTFET technology
S. Mohammad Ali Zanjani
a, Massoud Dousti
b,*, Mehdi Dolatshahi
aaDepartment of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran
bDepartment of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
A R T I C L E I N F O Keywords:
Low-power Universal Gm-Cfilter Inverter
Carbon nano tubefield-effect transistor (CNTFET)
A B S T R A C T
In this paper, a new low-power multi-mode Gm-C universalfilter is proposed in carbon nanotubefield-effect transistor (CNTFET) technology using only 11 inverters and 2 grounded capacitors. The proposed circuit re- duces the power consumption effectively due to the proper use of inverters as operational transconductance amplifier (OTA) blocks. Moreover, the center frequency and quality factor of the proposedfilter can be tuned electronically with low sensitivity values. The proposed circuit is simulated in HSPICE using 32 nm CNTFET technology parameters at0.2 V supply voltage, and its performance is compared with the circuit proposed in 32 nm CMOS technology. As simulation results show, for certain value of center frequency, the proposed CNTFET filter not only reduces the power consumption by 66%, but also extends the center frequency up to 54%, at the same power consumption value in comparison with 32 nm CMOS technology. Finally, the proposed CNTFETfilter benefits from a considerable reduction in chip area.
1. Introduction
In the recent years, continuous-time integrated filters have been widely used in both wired and wireless applications; these applications are categorized into major groups based on some considerations such as processing elements (active/passive), the type of input/output configu- ration, signal operation mode, frequency bandwidth, supply voltage, power dissipation and kind of integrated capacitors used in the circuit [1–10]. Various Gm-Cfilters have attracted extensive attentions due to their high frequency bandwidth, simple circuit realization, integration capability and electronic tunability of thefilter parameters such as center frequency (ω0) and quality factor (Q) [3–8]. Analog “Current-Mode” integrated circuits are widely used due to their lower required supply voltage as well as lower power consumption, better linearity behavior, fewer number of components, wide dynamic range and higher frequency bandwidth in comparison with their “Voltage-Mode” counterparts [9–17]. Mathematical operations on signals in current-mode circuits are simpler to perform in comparison with voltage-mode circuits [9,10].
Moreover, current-mode circuits can be used as direct cascading circuits to achieve the low/high input/output impedance requirements for real- izing analog filters [11,12]. In analog signal processing domain, the designer requires active filters that can properly operate with either current/voltage input or output signals [4,11,18–21]. Therefore, designing “Multi-Mode” universal filters that can generate all the
filtering responses (i.e., high-pass filter (HPF), low-pass filter (LPF), band-passfilter (BPF), band-stopfilter (BSF) and all-passfilter (APF)) in all modes of operation, using just one circuit configuration, is very challenging [4,7,10,17–25]. In other words, multi-mode Gm-C universal filters have attracted more attentions due to their reduced chip size and their lower power consumption and cost [4,18–21].
Due to the increasing demand for portable electronic devices and implantable medical systems, low power design of integrated circuits is a challenging task [2,4,6,8,14,16,24,25]. On the other hand, due to some problems that are caused by miniaturizing the dimensions of transistors beyond the 45 nm technology node, the conventional CMOS technology faces more complex issues and challenges. In fact, further miniaturization causes the following problems: process variations, leakage currents, the effects of short channel transistors, effect of high electricfield, limitations in lithographic process and quantum confinement effects [3,16,26–38].
Considering the above facts, nanometer integrated circuit designers should contemplate emerging technologies such as carbon nanotube field-effect transistor (CNTFET), which delivers some benefits such as lower power consumption, smaller size (nanoscale) and scalability [16, 27–38], MOSFET-like circuit behavior, ballistic transfer and higher mobility of carriers. Another important benefit of using CNTFET tech- nology includes the similar values of carrier mobility for both N-type and P-type CNTFET devices (μn¼μp) with the same transistor dimensions that leads to an identical driving capability and I-V characteristics
* Corresponding author.
E-mail addresses:[email protected](S.M.A. Zanjani),[email protected],[email protected](M. Dousti),[email protected](M. Dolatshahi).
Contents lists available atScienceDirect
Microelectronics Journal
journal homepage:www.elsevier.com/locate/mejo
https://doi.org/10.1016/j.mejo.2019.01.003
Received 15 March 2018; Received in revised form 24 October 2018; Accepted 6 January 2019 Available online 15 February 2019
0026-2692/©2019 Published by Elsevier Ltd.
–
[32–34]. Furthermore, lower values of intrinsic (parasitic) capacitances that leads to a higher frequency bandwidth and lower intrinsic delay for CNTFET integrated circuits in comparison with CMOS technologies are other advantages of CNTFET over CMOS technology [16,28–34,38].
Therefore, CNT devices with two major types of single-walled (SWCNT) (Fig. 1a) and multi-walled (MWCNT) structures are the most promising candidates to substitute CMOS technology nodes for less than 45 nm. Furthermore, conducting or insulating behaviors of CNTFET de- vices are determined by the chirality vector(m, n), which is the wrapping vector that the graphite sheet is rolled up along it as it is shown inFig. 1b [29–38]. The indices (m, n) specify the chiral angle of the carbon atoms along the nanotube structure. If (mn)6¼3k, where k is an integer number, the SWCNT acts as a semiconductor, else it shows a conductive (metallic) behavior [25,28,32–40].
Due to the high-speed carriers, quasi-ballistic transport and nanometer-scale structure, SWCNT is successfully used in the design of VLSI systems such as digital combinational logic gates, full adders, multiplexers, SRAM, etc. [25–28,39,40]. On the other hand, the design of analog integrated circuits such as OTA, current conveyor andfilter cir- cuits in the CNTFET technology is still demanding high research efforts [16,38,41].
This paper presents the design of a new low-power, inverter-based, universal, multi-mode Gm-C Filter in 32 nm CNTFET technology. The main purpose of this design is to introduce a new circuit topology plus a technology migration from CMOS to CNTFET in order to maximize the advantages of CNTFET technology. Therefore, the proper combination of these two benefits results in an improved overall performance of the proposed structure.
This paper is organized as follows. In section2, the physical structure and the descriptive parameters of CNT transistors are introduced. The use of an inverter block as an OTA circuit in both CMOS and CNTFET tech- nologies are analyzed and compared in section3, where the structure of the proposed Gm-Cfilter is also presented and its ability of multi-mode operation, as well as the sensitivity analysis is discussed in details. In
section 4, the results of circuit simulation, temperature analysis and Monte-Carlo simulation result are presented; in addition, the perfor- mance of the proposed circuit is compared with other reported designs.
Finally, in section5, some conclusions are presented.
2. CNTFET structure and parameters
A typical structure of a MOSFET-like CNTFET is shown inFig. 2. As it is obvious from thisfigure, a CNTFET is a three-terminal device con- sisting of semiconducting nanotubes between the source and drain ter- minals. These nanotubes act as the transistor channel that is controlled electrically via the gate terminal. The structural parameters used for modeling a CNTFET in HSPICE are summarized inTable 1.
As it is discussed in Refs. [25–28,35,38], the diameter of a carbon nanotube (DCNT) can be calculated from Eq.(1), in whicha¼2.49 Å is the distance between the centers of two adjacent nanotubes (lattice constant).
DCNT¼a ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi m2þn2þmn p
π (1)
The width of the CNT transistor (W) can be calculated using other structural parameters such as the diameter of the CNT (DCNT), number of CNTs (N) and inter-CNT pitch (S), as it is expressed in Eq.(2)[16,28,38, 41]:
W¼ ðN1ÞSþDCNT (2)
Analytical threshold voltage VT is expressed in Eq. (3a), and the Taylor series expansion ofVTshows a linear relationship withEgand an inverse relationship with the diameter of CNTFET Therefore, the threshold voltage can be simplified as it is given in Eq.(3b), where Vπ¼3.033 eV is the carbonπ–πbond energy andeis the electric charge [25–28,38,43].
Fig. 1.a) A typical single-walled carbon nanotube (SWCNT) structure, b) The chirality vector concept.
Fig. 2. Typical structure of a MOSFET-like CNTFET, a) cross section view, b) top view.
VT¼KTln
1
12eEgþ2kTαevD
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi eαevDkT þ24 q
eα2kTevD
(3a)
VT aVπ ffiffiffi3 p eDCNT
(3b) In Ref. [37], with the aim of CNTFET quantum simulation using non-equilibrium Green's function, the effects of changing the chirality vector and oxide thickness on the variations of V-Icharacteristics are investigated. On the other hand, the use of a reliable and computationally compact model for circuit design with considering the intrinsic CNTFET properties, parasitic capacitors and the effects of source to drain direct tunneling in a small gate length is important for the perspective of simulation and experimental results [25,36]. Therefore, in this paper, the CNTFET model proposed in Refs. [30,31] is used for circuit simulations.
Additionally, analytical current and voltage equations for the ballistic CNTFET devices based on some modifications on the equations discussed in Refs. [43,44] are presented as follows:
Rq ¼ h
4e26:45 KΩ (4)
WhereRqis the quantum resistance of the CNTFET. Equation(5) expresses the value of ON-current for a CNT transistor in saturation re- gion;ϕsis the analytical surface potential, which shifts the bands. For a small gate voltage,ϕsis close or equal toVG.
IonkT eRqln
1þe2eϕsEg2kT
(5) The transconductance and channel conductance of the CNTFET are obtained as follows:
gm¼
1
1þe2eφs2α2evDSEgkT 1 1þe2eφsEg2kT
1
Rq
∂φs
∂VGS
(6)
gds¼ α Rq
1þe2eφsþ22αkTevDSþEg1
(7) It is worth mentioning that to increase the transconductance of each transistor, the channel width should be increased; nevertheless, this also increases the parasitic capacitances and power consumption.
Fig. 3shows the parametergm=IDversus the normalized drain current (In ¼ID=
W L
) for both CNTFET and MOSFET transistors. As it is obvious in thisfigure, for identical specifications of aspect ratios of the transistors and the same bias conditions for both the CNTFET and its MOSFET counterpart, the CNTFET transistor generates a higher transconductance (gm) value for a specific drain current in comparison with its MOSFET counterpart. This shows the superiority of the CNTFET technology over CMOS technology in analog integrated circuit designs [45].
3. The proposed Gm-Cfilter structure
As it is mentioned before, the proposed Gm-Cfilter is designed based on the use of inverter circuit as an OTA block. Although inverters are usually used in digital circuits, but OTA blocks are used in various analog continuous-time applications such as low noise amplifiers, oscillators and filters, as it is discussed in Refs. [6,24,46,47]. In Ref. [46], a CMOS inverter is used as a voltage controlled OTA stage, according to the method of the Nauta and Seevinck [7]. In Ref. [6], the dual CMOS pair structure is used as an OTA block. In Ref. [8], an ultra-low-power CMOS OTA is used for low frequency Gm-C applications.
Giving the above facts, the inverter circuit shown inFig. 4is used as a transconductance block. The relationship between the input voltage and the output current is as follows:
iout¼gmvin¼
gmnþgmp vin (8)
Where gm is the total transconductance of the N-type and P-type transistors.
InFig. 5, the frequency responses of both CNTFET and CMOS in- verters in 32 nm technology are presented using the same supply voltage Fig. 3.(gm=ID) comparison between CNTFET and CMOS technologies.
Fig. 4. a) Inverter circuit. b) Inverter as a transconductance stage.
Table 1
CNTFET structural parameters used for circuit simulations [42].
Design Parameter Symbol Value
Physical channel length Lch 32 nm
The length of doped CNT source/drain extension region Lss(Ldd) 32 nm The mean free path in intrinsic CNT channel (due to non-
ideal elastic scattering)
Lgeff 200 nm The width of metal gate (Sub-lithographic pitch) Wgate 6.4 nm The dielectric constant of high-k top (planer) gate dielectric
material (HfO2)
Kgate 16
The thickness of high-k top (planer) gate dielectric material (HfO2)
Tox 4 nm
Diameter of CNT DCNT 1.49 nm
The distance between the centers of two adjacent CNTs Pitch¼S 20 nm The Fermi level of the doped source/drain tube Efi 0.6 eV The optical phonon backscattering mean-free-path in
metallic CNTs
λop 15 nm
The acoustic phonon backscattering mean-free-path in metallic CNTs
λap 500 nm
CNT work function ϕs 4.5 eV
The chirality vector of tubes (m, n) (19, 0)
The number of tubes in the device N 3
(typical)
value (0.2 V) and load capacitances. As it is obvious, the MOSFET inverter shows a gain amplitude of 10.92 dB at a gain-bandwidth (GBW) frequency of 6.7 MHz, while the CNTFET inverter shows a gain of 38.63 dB and a GBW frequency of 10.6 MHz for three nanotubes (N¼3) with the chirality vector (19, 0). In fact, in analog integrated circuit design, a better gain-bandwidth performance can be concluded for the CNTFET technology compared to CMOS technology.
Table 2compares the performances of the simulated OTAs in both CNT and CMOS technologies. As it is obvious inTable 2, the simulated OTAs in this paper use the lowest supply voltage value (0.2 V), while they present the best power-bandwidth trade-off at the same capacitive load value (0.1 pF). The CNTFET OTA has the maximum unity-gain fre- quency and slew-rate values at the similar power consumption in com- parison with its CMOS counterpart. Furthermore, the CNTFET OTA
consumes the lowest power compared to CMOS OTA at the same unity gain frequency. This makes the CNTFET OTA the best candidate for high- frequency and low-power analog integrated circuits design. The CNTFET OTA has an open-loop gain of 24.3 times higher than the gain value of its CMOS counterpart while consumes 37.4% less power at the same unity- gain frequency. Moreover, at the same power consumption value, the unity-frequency bandwidth of the CNTFET OTA is extended by 58.2, while a considerable increase in the slew-rate is obtained for a consid- erable reduction (i.e., 90%) of the chip size. It is worth mentioning that due to the existence of gain-speed trade-off in deep submicron technol- ogies including 32 nm CMOS technology, the intrinsic gain factor (gmro) degrades substantially [41]. Furthermore, due to a highergm=IDin the CNT technology, highergm and gain values are obtained for a CNTFET OTA at the same normalized drain current. As it is discussed in Refs. [16, 35,38], due to the ballistic transport of carriers in CNT technology, the effective mobility of a CNT transistor is higher than its CMOS counter- part; this leads to a considerable increase in the unity-gain bandwidth and speed (slew-rate) of the CNTFET OTA.
With regard to the above facts, as it is shown inFig. 6, a new current- mode universal Gm-Cfilter is proposed based on the method discussed in Ref. [48]. Thisfilter uses only 8 inverters (16 transistors) as OTA blocks.
In order to extend the ability of the proposed Gm-C current-modefilter to operate in all modes of operation, three inverter blocks should be added to the main current-mode core of the circuit, as shown with cross-lines in the left-hand side of Fig. 6. Accordingly, the proposed current-mode Gm-Cfilter circuit can be evolved to a multi-modefilter. FromFig. 6, Iin1, Iin2and Iin3are the input currents, andvin1, vin2and vin3are the corresponding input voltages;IoutandVoutrepresent the output current and voltage signals, respectively. Additionally, the proposed circuit uses two grounded capacitors to reduce the noise and eliminate the parasitic effects of active elements.
Assuming Iin1¼Iin2¼Iin3¼0, by applying Kirchhoff's current law (KCL) equations to the nodes v1 to v3, the following equations are obtained:
gm1vin1þgm2v3þSC1v1¼0 (9)
gm1v1þgm1v2¼0 (10)
gm1v2gm1vin2¼SC2v3þgm2v3 (11) gm2v3þgm1vin3þgm1vout¼0 (12)
The transfer function of the proposedfilter is obtained as follows:
(
vout¼N1ðSÞ vin3DðSÞ DðSÞ
DðSÞ ¼S2C1C2þSgm2C1þgm1gm2
N1ðSÞ ¼Svin2gm2C1þvin1gm1gm2 (13) Table 2
Performance comparison of the proposed CNTFET and CMOS inverter-based OTAs.
Performances of OTA inverter
First simulated CMOS OTA
Second simulated CMOS OTA
Proposed CNFET OTA
Technology 32 nm 32 nm 32 nm (m,
n)¼(19,0), N¼3
Power Supply 0.2 V 0.2 V 0.2 V
Open loop gain (A0) 10.92 dB 10.92 dB 38.63 dB Unit gain freq. (fT) 6.7 MHz 10.6 MHz 10.6 MHz Power Consumption
(pd)
40.3 nW 64.3 nW 40.3 nW
Transconductance (gm)
4.99μA/V 7.97μA/V 6.73μA/V
Phase Margin 73.6 73.8 89.3
THD 0.4% 0.4% 0.19%
PSRR 13.92 dB 13.92 dB 49.74 dB
Slew Rate 14.6 V/μs 14.7 V/μs 87 V/μs
Active OTA Area 26048 nm2 41216 nm2 2655 nm2 FOM¼ A0:fT
VDD:pd
1460 KHz/
(V.nW)
1452 KHz/
(V.nW)
56161 KHz/
(V.nW)
Fig. 6.Proposed universal current-mode (core circuit) and multi-mode (extended) Gm-Cfilter structure.
Fig. 5. Frequency response comparison of CNTFET and MOSFET inverters.
On the other hand, for current-mode filter, assuming vin1¼vin2¼vin3¼0, the current-mode transfer function of the proposed filter is obtained as follows:
Iout¼N2ðSÞ Iin3DðSÞ
DðSÞ N2ðSÞ ¼SIin2gm2C1þIin1gm1gm2 (14) According to the above equations, the responses of thefilter in all modes of operation are summarized as follows:
Current-mode and transresistance mode
Ifvin1¼vin2¼vin3¼0, thefilter responses are as follows:
AÞLPF:Iin1¼Iin;Iin2¼Iin3¼0 ⇒IoutðLPÞ Iin ¼gm1gm2
DðSÞ (15)
BÞBPF:Iin2¼Iin;Iin1¼Iin3¼0 ⇒IoutðBPÞ Iin ¼Sgm2C1
DðSÞ (16)
CÞHPF:Iin1¼Iin2¼Iin3¼Iin ⇒IoutðHPÞ
Iin ¼ S2C1C2
DðSÞ (17)
DÞBSF:Iin2¼Iin3¼Iin;Iin1¼0 ⇒IoutðBSÞ
Iin ¼ gm1gm2þS2C1C2 DðSÞ (18) EÞAPF: ðIin2¼2Iin;Iin3¼IinÞOrðIin2¼0;Iin3¼IinÞ;Iin1¼0
⇒IoutðAPÞ
Iin ¼ 1or gm1gm2Sgm2C1þS2C1C2
DðSÞ
(19)
Voltage-mode and transconductance mode
IfIin1¼Iin2¼Iin3¼0, thefilter responses are as follows:
AÞLPF:vin1¼vin;vin2¼vin3¼0 ⇒voutðLPÞ vin ¼gm1gm2
DðSÞ (20)
BÞBPF:vin2¼vin;vin1¼vin3¼0 ⇒voutðBPÞ vin ¼Sgm2C1
DðSÞ (21)
CÞHPF:vin1¼vin2¼vin3¼vin ⇒voutðHPÞ
vin ¼ S2C1C2
DðSÞ (22)
DÞBSF:vin2¼vin3¼vin;vin1¼0 ⇒voutðBSÞ
vin ¼ gm1gm2þS2C1C2
DðSÞ (23) EÞAPF: vin2¼2vin;vin3¼vin;vin1¼0
⇒voutðAPÞ
vin ¼ 1or gm1gm2Sgm2C1þS2C1C2 DðSÞ
(24)
Sensitivity analysis
Considering the denominator of the transfer function for the proposed circuit, the center frequency (ω0) and quality factor (Q) of the proposed Gm-Cfilter are obtained as expressed in Eqs.(25) and (26):
ω0¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffi gm1gm2 C1C2 r
(25)
Q¼ ffiffiffiffiffiffiffiffiffiffiffiffi gm1C2
gm2C1 s
(26) Sensitivity of the parametersω0andQparameters to the values of passive and active elements (i.e.,Candgm) are presented in Eq.(27)as follows:
8>
><
>>
:
SωC01¼SωC02¼1 2 Sωgm0
1¼Sωgm0
2¼1
2 SQgm1¼ SQgm2¼1
2 SQC1¼ SQC2¼1 2
(27)
It is worth mentioning that the sensitivity of allfiltering functions to
Fig. 7.Design algorithm for the proposedfilter circuit in CNTFET technology.
the values of gmiandCiare obtained as expressed in Eqs.(28)–(31); this implies another advantage of the proposed circuit that the summation of sensitivities of the proposed circuit to the values of active and passive elements is zero.
SLPFgm1 ¼ SLPFC1 ¼C1C2S2þgm2C1s
DðSÞ (28)
SLPFgm2 ¼ SLPFC2 ¼SBPFgm2 ¼ SBPFC2 ¼C1C2S2
DðSÞ (29)
SHPFgm1 ¼ SHPFC1 ¼SBPFgm1 ¼ SBPFC1 ¼gm1gm2
DðSÞ (30)
SHPFgm2 ¼ SHPFC2 ¼ðgm1þC1SÞgm2
DðSÞ (31)
4. Simulation results
The proposed universalfilter circuit is designed based on the design algorithm shown inFig. 7in which both structural and physical speci- fications of the CNTFETs are considered as inputs to the design algo- rithm. These specifications are as follows: structural specifications such as chirality vector (m, n), number of tubes (N), the values of supply voltage (VDD), passive capacitances (C1,C2) and physical specifications such as temperature (T), lattice constant (α), quantum resistance of the CNTFET (Rq) and CNT work function (φS). Then, based on the structural and physical specifications of the nanotube technology, the main design parameters as well as the bias voltages and currents are calculated.
In the next step, based on the calculated design parameters and bias conditions, the main performance measures of the proposed universal filter, such as center frequency, power consumption, etc. can be calcu- lated. Therefore, if the computed performances meet the pre-defined requirements, the design procedure is terminated. Nevertheless, if some performance measures do not meet the design requirements, the design variables (structural specifications) are modified and the design algorithm is run using the updated design variables. Finally, this design process continues until all of the performance measures are met.
InTable 3, the simulation results of the proposed Gm-C circuit are summarized (assumingC1¼C2¼1 pF), where the performances of the proposed circuit in both MOSFET and CNTFET technologies are compared.
As it is obvious fromTable 3, the proposed circuit in CNTFET tech- nology shows 54% extension in the center frequency, while the active chip area is considerably reduced (99%) in comparison with its 32 nm CMOS counterpart, for the same values of power consumption and supply voltage. For the same value of the center frequency, the CNTFETfilter circuit consumes only 66% of power consumed by the CMOSfilter, and the active chip area is reduced by 92.7% in comparison with CMOS technology. By properly selecting the chirality vector and the number of nanotubes, power consumption may decrease further. In addition, the
proposed CNTFETfilter circuit shows a superiority in terms of FOM performance parameter over other designs, and it is observed that the best performance is obtained forN¼3 and the chirality vector (19, 0).
Figs. 8–11show the simulation results of the frequency response for the proposed CNTFET inverter-based universal Gm-Cfilters in all modes of operation for 1.1 MHz center frequency at0.2 V supply voltage, using N¼3 nanotubes with the chirality vector (19, 0).
There is a good compliance between the theoretical results in MAT- LAB and HSPICE circuit simulations. As it is expressed in Eqs.(32)–(35), considering the assumedgmvalues for N and P CNTFET transistors, the center frequency of the circuit is mathematically calculated 1.1 MHz in MATLAB and 1.07 MHz in HSPICE; this shows a close agreement that confirms the good design accuracy of the proposed circuit.
Theoretical:gm:inverter¼gm:nchþgm:pch¼3450nA
Vþ3450nA
V ¼6900μA V
(32)
f0¼ 1 2π
ffiffiffiffiffiffiffiffiffiffiffiffiffiffi gm1gm2
c1c2 r
¼1098 kHz 1:1 MHz (33)
Table 3
Performance comparison of the proposed Gm-Cfilters in 32 nm MOSFET and CNTFET technologies.
TECH. Aspect ratio or N, (m, n)
VDD, VSS (V)
Dissipated Power (Pd) nW
Central Freq. (f0) KHz
Quality Factor (Q)
Min Area of Transistors μm2
FOM¼(f0.Q)/(Pd.Area) KHz/nW.μm2
CMOS 32 nm 400 nm=45 nm 0.2 678.8 1100 0.73 0.396 2.987
CMOS 32 nm 2606 nm=45 nm 0.2 447.5 712.85 0.71 2.58 0.44
CNTFET 32 nm
N¼3, (m, n)¼(19, 0) 0.2 447.5 1100 0.97 0.0289 82.5
CNTFET 32 nm
N¼11, (m, n)¼(15, 0)
0.2 86.6 217 0.96 0.141 17.06
CNTFET 32 nm
N¼5, (m, n)¼(15, 0) 0.2 39.3 100 0.95 0.0571 42.25
CNTFET 32 nm
N¼3, (m, n)¼(13, 0) 0.2 2.61 6.46 0.96 0.0289 82.21
Fig. 8.Frequency response of the proposed universal current-modefilter.
Fig. 9.Frequency response of the proposed voltage-mode universalfilter.
Circuit simulations:gm:inverter¼gm:nchþgm:pch¼6730μA
V (34)
f0¼ 1 2π
ffiffiffiffiffiffiffiffiffiffiffiffiffiffi gm1gm2
c1c2 r
¼1071 kHz1:07 MHz (35)
4.1. Filter tunability
As it is shown inFig. 12, by changing the supply voltage from 0.16 V to 0.24 V, the center frequency of the band-passfilter can be varied in the range of 300 kHz to 3.3 MHz. According to Eq.(25), by increasing the supply voltage, the transconductance of the inverters and the center frequency of thefilter increase; nevertheless, considering Eq.(26), the quality factor remains constant.
In order to investigate the sensitivity of thefilter's performances to the values of capacitorsC1andC2, simulation results of sensitivity analysis are shown inFig. 13, in which the capacitances are varied in the range of 10% of their typical values of 1 pF. As it is obvious inFig. 13, the center frequency varies in the range of10% of its typical value of 1.1 MHz.
Due to the fact that the parasitic capacitances, which are imposed by the circuit layout, have some impacts on the circuit performance, the performance degradation induced by the parasitic capacitances is investigated, and the results are summarized inTable 4, and the overall behavior is illustrated inFig. 14. FromTable 4, the effects of parasitic capacitances are more visible for thefilter's capacitance values of less than 1 fF. In Eq.(25), the center frequency increases if the values of the filter's capacitances decrease; but as it is clear inFig. 14, forfilter ca- pacitances of less than 1 fF, the center frequency does not increase line- arly due to the appearance of parasitic capacitances that are comparable withfilter's capacitances. This issue justifies the performance degrada- tion for the proposedfilter due to the capacitive parasitic effects. In order to avoid such parasitic effects in the design of the proposedfilter, the values ofC1andC2are chosen to be 1 pF that is far from the values of parasitic capacitances approximated in this design, i.e., 50-70 aF.
Fig. 11. Frequency response of the proposed transresistance-mode univer- salfilter.
Fig. 12. Variations of the band-passfilter's center frequency versus different supply voltage values.
Fig. 13.Sensitivity of the center frequency of the band-passfilter to the values of external capacitances.
Fig. 10. Frequency response of the proposed transconductance-mode univer- salfilter.
Table 4
Center frequency variations due to changing thefilter's capacitances considering parasitic effects.
C1¼C2 1 pF 0.1 pF 10 fF 1 fF 0.1 fF 10 aF
Center frequency
1.1 MHz 11 MHz 110 MHz 1 GHz 6.8 GHz 14.8 GHz
Fig. 14.Center frequency performance degradation due to thefilter's parasitic capacitances.
4.2. Temperature and Monte-Carlo analysis
As it is discussed in Ref. [49], the effects of self-heating and non-self-heating of carbon nanotubes on the current-voltage character- istics, delay and cut-off frequency of CNTFET transistors are investigated by solving a one-dimensional equation of thermal conductivity using finite difference method. It is shown that the performance quality degradation for CNTFETs is much less than MOSFETs, which justifies the good electro-thermal properties of CNTFET technology [43,49,50]. As it is discussed in Ref. [50], the thermal conductivity of a SWCNT transistor shows a linear temperature dependency (see Fig. 15). The effect of temperature variations in the range of (10C toþ40C) on the fre- quency response of the proposedfilter is simulated. The results of tem- perature analysis presented in Fig. 16 verify that increasing the temperature leads to a quasi-linear increase in center frequency and power consumption for the proposedfilter.
For investigating the effects of non-idealities of non-uniform growth of carbon nanotubes in the fabrication process and inaccurate litho- graphic effects (i.e., dimensions of CNTFET transistors and effective mobility of carriers) on the performances of CNTFETs, the Monte-Carlo analysis is performed. Therefore, the effects of threshold voltage varia- tions in the range of2.5% of its nominal value are analyzed in HSPICE, based on the method discussed in Refs. [51,52], which is shown in Fig. 17. FromFig. 17, the center frequency varies between 961 KHz and 1.19 MHz for 70 different iterations around a mean value of 1.0774 MHz.
Fig. 18shows the Monte-Carlo simulation results of the frequency response for the pitch variations in the range of 18–22 nm.Figs. 19 and 20show the Monte-Carlo simulation results of the transient responses for the proposed high-pass and low-passfilters, respectively; these results verify the good performance and design robustness of the proposed CNTFETfilter. Moreover, the Monte-Carlo simulation results of10%
pitch variations for the center frequency performance of the proposed filter is analyzed and shown inFig. 21.
The dependencies of thefilter's performances on CNTFET structural parameters, such as number of nanotubes, diameter of CNT and pitch parameter, are investigated and simulated in HSPICE. For example, by changing the pitch parameter in its maximum allowable range from 10 nm to 27 nm, the center frequency of the proposed filter varies
Fig. 15.Frequency response variations versus different temperatures for the proposed band-passfilter.
Fig. 16. Power and center frequency variations due to the changing of oper- ating temperature.
Fig. 17.Monte-Carlo simulation results for the effect of 2.5% threshold voltage variations on the center frequency of the proposed band-passfilter.
Fig. 18. Monte-Carlo simulation results of frequency response of the proposed universalfilter for pitch variations.
Fig. 19.Monte-Carlo simulation results of transient response of the proposed high-passfilter for pitch variations in the range of 18-22 nm.
between 977 kHz and 1.125 MHz, and power consumption varies be- tween 405.3 nW and 455.7 nW, as summarized inTable 5.
Similarly, increasing the diameter of a carbon nanotube by control- ling the chirality vector shows an exponential increase in the center frequency and power consumption of the proposedfilter, as summarized inTable 6and illustrated inFig. 22.
One of the major structural CNTFET parameters, which has a signif- icant impact on the performance of the proposedfilter, is the number of nanotubes. Therefore,Nvaries from 3 to 15, assuming afixed chirality vector (m, n)¼(19, 0) for all CNT devices in the proposed band-pass filter. The simulation results for the variations of major filter perfor- mances, such as center frequency (ω0), power consumption and total harmonic distortion (THD%) due to the changing ofN, are illustrated in Figs. 23–25. By increasing the number of nanotubes, power consumption and center frequency of thefilter increase in a quasi-linear manner.
Fig. 25indicates the variations of total harmonic distortion (THD%) versus the number of nanotubes. In order to achieve the minimum value
ofTHD, the designer may selectN5, which leads to the minimum value ofTHDof only 1.16%.
4.3. Comparison with other designs
Finally,Table 7summarizes the performances of the proposedfil- ter, where they are compared with other previously published designs.
The proposed circuit has the lowest power consumption and supply voltage values in comparison with other reported designs. Moreover, the proposedfilter implements a universalfilter with the capability of working in all modes of operation, while some other designs cannot operate in all modes or cannot generate allfiltering responses in a reduced chip size. The performances of the proposed universalfilter are compared with other reported designs in the CNTFET technology.
As it is clear inTable 7, the proposed universalfilter has the lowest power consumption and supply voltage values in comparison with [56, 57], while the circuits discussed in Refs. [56,57], suffer from the lack of multi-mode operation or generating universal filtering responses [57]. On the other hand, the proposed circuit suffers from the Fig. 20. Monte-Carlo simulation results of transient response of the proposed
low-passfilter for pitch variations in the range of 18-22 nm.
Fig. 21. Monte-Carlo simulation results for the effect of10% pitch variations on the center frequency of the proposed band-passfilter.
Table 5
Effects of changing the pitch parameter on the performances of the proposed filter.
Pitch (nm) 10 14 17 20 24 27
Center frequency (KHz) 977 1000 1040 1100 1115 1125 Power Consumption
(nW)
405.3 431.5 441.4 447.5 452.6 455.7
Table 6
Effects of chirality vector variations on the performances of the proposedfilter.
Chirality vector (10, 1) (11, 3) (13, 0) (11, 8) (17, 0) (19, 0) (20, 2) (30, 2)
DCNT(nm) 0.839 1.012 1.0303 1.309 1.347 1.506 1.670 2.461
Center frequency (KHz) 0.138 5.2 7.13 214 307 1100 2690 15500
Power Consumption (nW) 0.058 1.93 2.61 86.7 124 447.5 1230 11370
Fig. 22. Center frequency and power consumption variations due to changing of CNT's diameter.
Fig. 23. Variations of the band-passfilter's center frequency versus different number of nanotubes.
relatively higher THD value in comparison with [4,48], but the circuit discussed in Ref. [48], is not a universalfilter and implements only the band-pass frequency response, while both the circuits in Refs. [4,48]
suffer from the higher power consumption in comparison with the proposed circuit. Giving the above facts, the main contribution of this work is the proper combination of the benefits of the new filter structure design and the benefits of the technology migration (CMOS to CNTFET). The former improves the circuit performances and spec- ifications such as universal frequency responses, multi-mode operation and tunability of the filter, and the latter results in a better power-bandwidth trade-off for the proposed circuit.
5. Conclusions
In this paper, a new CNTFET-based, low-power universal Gm-Cfilter was designed in current-mode using inverters as OTA blocks. The pro- posed current-modefilter has a reduced chip size and low power con- sumption, and is able to function in all modes of operation by adding only three inverters to the main current-mode core circuit. Actually, inclusion of these three inverters enables the proposed circuit to be used with all input/output signal types (current/voltage) without the requirement of any additional I/V converter circuits. The center frequency and quality factor of the proposed filter can be tuned electronically with a low sensitivity to the values of active and passive components. The perfor- mance of the proposed circuit was simulated in HSPICE using 32 nm CNTFET technology parameters and compared with the performance of the proposed circuit in 32 nm CMOS technology. It was found that by proper selection of CNTFET design parameters, such as chirality vector and the number of carbon nanotubes, improved total harmonic distortion as well as power-bandwidth trade-off can be achieved. Moreover, in order to further decrease the power consumption, the sub-threshold technique can be used in the design process and the performance of the proposed circuit can be investigated in future studies. Finally, the Fig. 24.Center frequency and power dissipation variations versus changing the
number of nanotubes (N).
Fig. 25. THD% variations versus increasing the number of nanotubes for the proposed band-passfilter.
Table 7
Performance comparison of the proposedfilter with other reported designs.
Ref Technology No of ABBs(Active Building Blocks)
No of C/
R
Supply Voltage
Power diss.
Universal Multi- mode
Quality Factor
THD
[4] 0.18μm-
CMOS
2 gm for biquad. 2C/0R – 309μW ✓ ✓ – 0.74%
[6] 0.35μm-
CMOS
4 OTAs 4C/0R 3.3 V 178μW LP ✓ – 40 dB at 400 mV
[9] 0.35μm-
CMOS
Direct design – 1.5 V 6.6 mW LP-HP-BP C.M. 0.707 1.74% (BP)
[11] 0.35μm- CMOS
3 DVCCs 2C/3R 1.5 V 5.67 mW LP-BP-HP/
BS
✓ 0.707 1.3%
[15] 0.35μm- CMOS
2 DCCIIs 1C/3R 1.25 V 1.3 mW AP ✓ – –
[17] 0.13μm- CMOS
2 ICIIsþ1MOSFET 1C/0R 0.75 V 2.75 mW ✓ C.M. – 0.233%
experimental [20] 0.18μm-
CMOS
1 FDCCIIþ1 DDCC 2C/6R 0.9 V – ✓ ✓ 1 1% at 150 mV
applied [21] 0.35μm-
CMOS
3 DVCCs 2C/3R 1.5 V 3.47 mW ✓ V.M. 1 0.932 until 13%
[48] 0.35μm- CMOS
4 OTAs 4C/0R 2.5 V 800μW BP ✓ – 0.46%
[53] 0.18μm- CMOS
1 VDTA 3C/1R 0.9 V 540μW LP-HP-BP ✓ 0.5,1,5 4% at 400 mV
applied 7% at 200μA applied [54] 0.25μm-
CMOS
2 OTAs 3C/0R 1.8 V – LP-HP-BP ✓ – 4% for 300 mV
[55] 0.18μm- CMOS
3 DDCCs 2C/4R 0.9 V – ✓ V.M. 1–8 3% at 400 mV
applied
[56] 32 nm-
CNTFET
2 ICC-II 2C/3R 0.9 V 54μW ✓ V.M. – –
[57] 32 nm-
CNTFET
2 ICC-II 2C/2R 0.7 V 430μW BP V.M. 0.12 –
This WORK
32 nm- CNTFET
8/11 Inverters 2C/0R ±0.2V 447 nW ✓ ✓ 0.97 ≥1.16%
theoretical results showed a very good agreement with the results ob- tained from circuit simulations, which verify a good design accuracy.
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