PPT PowerPoint Template - KNTU

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Nyquist Rate ADCs

Dr. Hossein Shamsi

K.N. Toosi University of Technology

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Content

 Sample & Hold Circuits

 Voltage Comparators

 Dual-Slope ADC

 Flash and Folding & Interpolating ADCs

 SAR ADC

 Two-Step ADC

 Pipelined ADC

 Time Interleaved ADC

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Dual Slope (Integrating) ADC

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Dual Slope (Integrating) ADC

It is simply proven that “Bout” denotes the desired output code.

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Content

 Sample & Hold Circuits

 Voltage Comparators

 Dual-Slope ADC

 Flash & Interpolating ADCs

 SAR ADC

 Two-Step ADC

 Pipelined ADC

 Time Interleaved ADC

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Flash ADC

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Offset problem

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Other Issues

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Reducing Complexity

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Interpolation

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Concept

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Example: Interpolating Factor of 4

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Content

 Sample & Hold Circuits

 Voltage Comparators

 Dual-Slope ADC

 Flash & Interpolating ADCs

 SAR ADC

 Two-Step ADC

 Pipelined ADC

 Time Interleaved ADC

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Flow Graph for the Successive-Approximation Approach

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D/A Converter-Based Successive-

Approximation Converter

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Another Flow Graph for the Successive-Approximation

Approach

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Successive Approximation Register ADC

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Implementation

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Sampling Phase (5-bit Example)

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Bit5 Test (MSB)

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Bit4 Test (Assuming bit5=0)

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Speed Estimate

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Limitations

•Conversion rate is N times smaller than the clock frequency.

•Conversion rate typically limited by finite bandwidth of RC network during sampling and bit-tests

• For high resolution, the binary weighted capacitor array can become quite large

– E.g. 16-bit resolution, C

_total

~100pF for reasonable kT/C noise contribution

• If matching is an issue, an even larger value may be needed

– E.g. if matching dictates C

_min

=10fF, then 2

¹⁶

C

_min

=655pF

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High Performance Example

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Low Power Example

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Content

 Sample & Hold Circuits

 Voltage Comparators

 Dual-Slope ADC

 Flash & Interpolating ADCs

 SAR ADC

 Two-Step ADC

 Pipelined ADC

 Time Interleaved ADC

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General Concept of Multi-Step

Conversion

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Analysis

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Cont’d

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More illustration

Aggregate=total

Pronounced= هدش هتخانش

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Limitations

Commensurate=equal

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Input to Fine Quantizer with Gain

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An 8-bit Ideal two-step ADC

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An 8-bit two-step ADC with Digital

Error Correction

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Content

 Sample & Hold Circuits

 Voltage Comparators

 Dual-Slope ADC

 Flash & Interpolating ADCs

 SAR ADC

 Two-Step ADC

 Pipelined ADC

 Time Interleaved ADC

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Pipeline ADC Block Diagram

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Pipeline ADC Characteristics

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Stage Analysis

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Stage Model with Ideal DAC

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"Residue Plot" (2-bit Sub-ADC)

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Upper Bound for Stage Gain

Example: First stage with 2-bit sub-ADC, followed by 2-bit backend ADC

D

_out

=D+G

^-1

D

_b

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Issue with G=2 B

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Idea #1: G slightly less than 2 B

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Idea #2: G =2 B-1

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Idea #3: G=2 B , Extended Backend

Range

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Variant of Idea #2: "1.5-bit stage“

G =2

^B-1

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1.5-bit Gain Stage

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1.5-bit Gain Stage non-idealities

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Block diagram of a 12-bit pipelined ADC

Pipelined ADC with four 3-bit stages (each

stage resolves two bits).

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Block diagram of a B×N-bit pipelined ADC

+ x 2B

-



B+1 bits stage 2 ...

ADC DAC

stage 1 stage N

B+1 bits B+1 bits B+1 bits

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AD9042

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Sampled data n-bit residue generator (N = 2

ⁿ

)

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Pipelined ADC (composed of 2-bit gain-stages)

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Pipelined ADC (composed of 1.5-bit gain-stages)

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1.5-Bit Stage Implementation

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Residue Plot

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Content

 Sample & Hold Circuits

 Voltage Comparators

 Dual-Slope ADC

 Flash & Interpolating ADCs

 SAR ADC

 Two-Step ADC

 Pipelined ADC

 Time Interleaved ADC

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Time-Interleaved ADC