A 4.86 W/Channel Fully Differential Multi-Channel Neural Recording System
Taeju Lee1, Ji-Hyoung Cha2, Su-Hyun Han2, Seong-Jin Kim2, and Minkyu Je1
1School of Electrical Engineering, Korea Advanced Institute of Science and Technology, (KAIST), Daejeon, Korea
2School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST), Ulsan, Korea {taeju.lee, mkje}@kaist.ac.kr
Abstract— This paper presents a fully differential multi-channel neural recording system. The system consists of four key blocks which are a low-noise amplifier (LNA), programmable gain amplifier (PGA), buffer, and successive approximation register ADC (SAR ADC). The input stage of the OTA used in LNA is designed as the inverter-based structure for improving the current efficiency. For an energy efficient system, the dual sample-and-hold (S/H) structure is applied to the SAR ADC.
Each channel consumes the power of 4.86 W/Channel and achieves an input-referred noise of 2.58 Vrms. The implemented IC operates under a 1-V supply voltage for core blocks and 1.8- V for output digital buffers. The system is implemented in a standard 1P6M 0.18-m CMOS process.
Keywords—Neural recording system, low-noise amplifier, inverter-based input stage, energy efficient system.
Ⅰ.INTRODUCTION
The low-power, low-noise multi-channel neural recording system is one of the many parts required to perform brain research. Thanks to the development of a multi-channel electrode array, the recorded neurons have steadily increased.
Accordingly, the number of recording circuits has to increase.
In the case of the implantable biomedical devices, the system must be driven with low power to prevent necrosis caused by heat. At the same time, the system should be designed to have low noise characteristics to measure microscale neural signals. The neural signals are distributed in the frequency band from sub-1 Hz to several kHz. This band is vulnerable to the interference such as power lines and stimulation signals.
Therefore, the recording system that is robust against the interference should be designed. In this paper, we present a low-power, low-noise fully differential multi-channel neural recording system for implantable biomedical devices.
Ⅱ.SYSTEM ARCHITECTURE
Fig. 1 shows the proposed system architecture, which consists of analog front-ends (AFEs), analog multiplexers (AMUXs), dual SAR ADCs, digital multiplexers (DMUXs), a bias circuit, and an output driver. To implement the 64- channel recording system, eight unit blocks (Set N, N=1-8) are used. Each unit block consists of LNAs, PGAs, buffers, an AMUX, and a 10-bit dual SAR ADC. The AFE that consists of LNA, PGA, and buffer is designed as a fully differential structure. In the unit block, eight AFEs share an AMUX and an ADC. An AMUX accepts eight channels and sends two channels to the ADC through selection signals SELA and SELB. After the digitization of neural signals, the channel selection is performed by four DMUXs, which are controlled through SX1 and SY1. The final channel selection is conducted by a DMUX controlled by SX2 and SY2. The output signals are 11 bits consisting of one end-of-conversion (EOC) signal and 10-bit data. The overall system is driven with 1-V and 1.8-V supply voltages. The 1-V supply voltage is to operate AFEs, AMUXs, ADCs, DMUXs, and a bias circuit.
The 1.8-V supply voltage is used for the output driver, which up-shifts the voltage level of the final output bits to interface with the field-programmable gate array (FPGA). The LNA and PGA are implemented as a capacitively-coupled structure. The OTA GM1 used in the LNA is shown in Fig. 1.
The input stage of the GM1 is implemented as the inverter- based structure, reported in [1], [2], for improving the current efficiency. The output DC bias point of the GM1 is set by one common-mode feedback (CMFB) OTA. The input stage of the OTA GM2 used in the PGA is designed as only PMOS pair.
The voltage gains of the LNA and PGA are set by the ratio of C1/C2 and C3/C4, respectively. The input DC bias points of GM1 and GM2 are set by R1 and R2, respectively. The R1 and R2 are implemented using two diode-connected MOSFETs for area efficient design while achieving the high resistance.
The output buffer for driving the ADC input is implemented as a rail-to-rail type based on [2].
In the digitization stage, the dual S/H structure in [2] is employed to increase the sampling time for the A/D conversion, which can reduce the power burden on the buffer.
To lower the power consumption in the ADC, the delay chain based time domain comparator, that is reported in [3], is adopted as shown in Fig. 2. In this work, the 4-stage delay chain is used to convert the input signals of VDAC and VDAC
This research was supported by the Convergence Technology Development Program for Bionic Arm (2017M3C1B2085296) and the Brain Research Program (2017M3C7A1028859) through the National Research Foundation Korea (NRF) funded by Ministry of Science and ICT.
Neural Data
11-Bit
Digital MUX (4-to-1)
1 1
DVSS DVDD HDVDD
Output Driver Set 2
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1
GM1 C3
C3 C4 C4 R2
R2
GM2 VOUT- VOUT+
VCM VCM
VCM VCM
10-Bit Dual SAR ADC SELA Ch1
2345678
CLK Set 1
SELB Ch1-4
Ch5-8 2 Analog MUX (4-to-1)
11-Bit
11-Bit 11-Bit
11-Bit
Set 4
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1 OTA
C3
C3 C4 C4 R2
R2 OTA
VOUT-
VOUT+
1
1
VCM VCM
VCM VCM
VIN+
VIN- C1
C2 C2
C1 R1
R1
GM1 C3
C3 C4 C4 R2
R2
GM2 VOUT- VOUT+
VCM VCM
VCM VCM
Ch17 18Set 3192021222324
Ch17-20
Ch21-24 11-Bit
11-Bit 11-Bit
11-Bit Set 5 / Set 6 / Set 7 / Set 8
VIN1 VREF1 VREF2
VREF8
VIN2 VIN3
VIN63 VIN64
Digital MUX (4-to-1) Digital MUX (4-to-1)
11-Bit SX1SY1
SX1SY1
SX2SY2
SELASELB SX1 SY1 SX2 SY2
64-Channel Neural Recording System
Bias Circuit 2 Analog MUX (4-to-1) 10-Bit Dual SAR ADC
SELA CLK SELB BUF
BUF
GM1 AVDD
AVSS VB
VI+ VI-
INV1 INV2
VO+ VO-
RX
CX RX CX
VCMFB
Fig. 1. Architecture of the multi-channel neural recording system.
978-1-5386-7960-9/18/$31.00 ©2018 IEEE 68 ISOCC 2018
to the delay difference based on the reference clock CLKB. The dual operation of the ADC is performed using two capacitive DACs (CDACs) that are implemented as the split array for area efficient design. The unit capacitance used in the CDAC is 150 fF with MIM structure occupying the area of 72 m2. Fig. 3 shows the schematic of the 10-bit dual SAR ADC and timing diagram for channel conversion.
Ⅲ.MEASUREMENT RESULTS
The IC is fabricated in a 1P6M 0.18-m CMOS process.
The active area of a 64-channel recording system is 9.4 mm2. The power consumption of a single channel, including LNA, PGA, buffer, and ADC, is 4.86 W/Ch. The system gain is measured from 61 dB to 74 dB with the bandwidth of 10 kHz.
Fig. 4 shows the measured frequency response and time domain results corresponding to each gain. The input- referred noise (IRN) is measured as 2.58 Vrms when integrated from 10 Hz to 10 kHz as shown in Fig. 5. The noise efficiency factor (NEF) is calculated as 2.19, resulting in the power efficiency factor (NEF2VDD) of 4.80. The total harmonic distortion of the AFE is measured as 1.5 %, corresponding to 36.5 dB that is measured using 100 Vpp
input at 1 kHz as shown in Fig. 6(a). The output power
spectrum of the ADC is measured using 1 Vpp input at 1 kHz, resulting in the effective number of bits (ENOB) of 9.63 bit, signal-to-noise and distortion ratio (SNDR) of 59.76 dB, and spurious-free dynamic range (SFDR) of 70.7 dB as shown in Fig. 6(b). The differential nonlinearity (DNL) and integral nonlinearity (INL) are measured as 0.53/0.65 LSB and
3/0.08 LSB respectively as shown in Fig. 6(c) and (d). The clock frequency for ADC operation is set to 2.5 MHz. Fig. 7 shows the die micrograph and performance summary.
Ⅳ.CONCLUSION
The implemented IC consumes the power of 4.86 W/Ch and occupies the area of 0.13 mm2/Ch while achieving the input noise of 2.58 Vrms by employing the inverter-based structure in the LNA input stage. The power burden on the buffer is reduced by using the dual S/H technique while maintaining the sampling rate of 200 kS/s.
REFERENCES
[1] D. Han et al., “A 0.45 V 100-Channel Neural-Recording IC With Sub-
W/Channel Consumption in 0.18 m CMOS,” IEEE TBioCAS, vol. 7, no. 6, pp. 735-746, Dec. 2013.
[2] X. Zou et al., “A 100-Channel 1-mW Implantable Neural Recording IC,” IEEE TCAS–Ⅰ, vol. 60, no. 10, pp. 2584-2596, Oct. 2013.
[3] S.-K. Lee et al., “A 21fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface,” IEEE JSSC, vol. 46, no. 3, pp. 651-659, Mar. 2011.
Phase Detector Voltage-Controlled
Delay Chain VP
VN
CLKB VT
Voltage-Controlled Delay Chain VP
VN
CLKB VT
Time Domain Comparator
CLK CLKB
CLKB VDAC+
VDAC-
VDAC+
VDAC-
COMPOUT
Voltage-Controlled Delay Chain DVDD
DVSS VP
VN
CLKB VT
Fig. 2. Block diagram of the time domain comparator [3].
Time Domain Comparator Time Domain Comparator
1C 1C 2C 4C 8C 1C 2C 4C 8C 16C CS
1C 1C 2C 4C 8C 1C 2C 4C 8C 16C
CS HI
VCMLO
VIN2- VIN2+
GND SRST SB SB SRST GND Capacitive DAC-2
HI VCM LO 1C 1C 2C 4C 8C 1C 2C 4C 8C 16C
CS
1C 1C 2C 4C 8C 1C 2C 4C 8C 16C
CS
HI VCM LO
VIN1- VIN1+
GND SRST SB SB SRST GND Capacitive DAC-1
HI VCM LO
Dual SAR Logic
CLK CLK
VDAC2- VDAC2+
VDAC1- VDAC1+
COMPOUT2 COMPOUT1
D9-1 - D0-1
D9B-1 - D0B-1
D9-1 - D0-1
D9B-1 - D0B-1
D9-2 - D0-2
D9B-2 - D0B-2
D9-2 - D0-2
D9B-2 - D0B-2
Capacitive DAC-1 Capacitive DAC-2
Ch1 Ch1 Ch2 Ch2 Ch3 Ch3 Ch4
Ch5 Ch5 Ch6 Ch6 Ch7 Ch7
Ch8
Sampling (13 CLK) Conversion (10 CLK) Reset ( 1CLK)
Fig. 3. Schematic of the 10-bit dual SAR ADC and timing diagram.
Frequency [Hz]
Gain [dB]
100 101 102 103 104 105 55
60 65 70
Time [ms]
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0
-0.1 -0.2 0.1 0.2
Output [V]
Fig. 4. Measured frequency response (left) and time domain results corresponding to each gain with a 100 Vpp input at 1 kHz (right).
Frequency [Hz]
101 102 103 104
10-8 10-7 10-6
IRN [V/ Hz]
Time [ms]
IRN [μV]
5 10 15 20 25 30
0 1 2 3 4
-1 -2 -3 Integrated IRN = 2.58 μVrms (10 Hz – 10 kHz)
Fig. 5. Measured input-referred noise in the frequency domain (left) and time domain (right).
Frequency [Hz]
Output [V]
102 103 104
10-3 10-2 10-1
-36.5 dB VIN = 100μVpp @ 1 kHz
Frequency [kHz]
Power [dBW]
0 2 4 6 8 10 12 14 16 18 20
0 -20 -40 -60 -80 -100 -120
ENOB = 9.63 bit SNDR = 59.76 dB SFDR = 70.7 dB
(a) (b)
Digital Output Code
DNL [LSB]
0 100 200 300 400 500 600 700 800 900 1000 0.5
-0.5 0
Digital Output Code
INL [LSB]
0 100 200 300 400 500 600 700 800 900 1000 01
2 3
(c) (d)
Fig. 6. (a) Measured total harmonic distortion of the analog front-end, (b) Output power spectrum of the ADC, (c) Differential nonlinearity (DNL), and (d) Integral nonlinearity (INL).
[1] [2] This work
Process 0.18-m 0.18-m 0.18-m
Supply Voltage 0.45-V 1-V 1-V
Supply Current *2.09 A/Ch *4.54 A/Ch 4.86 A/Ch
Gain 52 –55.6 dB 54.8 –60.9 dB 61 –74 dB
Bandwidth 10 kHz 5.1 kHz 10 kHz
Input-Referred
Noise 3.2 Vrms 4 Vrms 2.58 Vrms
NEF 1.57 1.9 2.19
NEF2VDD 1.12 3.6 4.80
A/D Type SAR SAR SAR
Sampling Rate 200 kS/s 24.5 –245 kS/s 200 kS/s
Resolution 9 bit 9.5 bit 10 bit
ENOB 8.27 bit 8.3 bit 9.63 bit
SNDR – 51.5 dB 59.76 dB
SFDR – – 70.7 dB
DNL +0.5 LSB
-0.5 LSB +0.55 LSB -0.55 LSB
+0.53 LSB -0.65 LSB
INL +1 LSB
-1 LSB +1.2 LSB
-1.2 LSB +3 LSB -0.08 LSB
Power/Ch 0.94 W/Ch *4.54 W/Ch 4.86 W/Ch
Area/Ch – – 0.13 mm2/Ch
* Calculated based on the reported data
Analog Front-End
Analog Front-End Digital Block
2.9 mm
3.24 mm
Fig. 7. Die micrograph (left) and performance summary (right).
