Analysis of the Effects of Differential Integrated Antennas on Voltage Responsivity of Sub- terahertz CMOS Detectors
Moon Jeong Lee
1, Ha Neul Lee
2, Hyo Jin Lee
3, Ga Eun Lee
4, Ju Hee Son
5, and Jong Ryul Yang
aDepartment of Electronic Engineering, Yeungnam University
E-mail: 1[email protected], 2[email protected], 3[email protected], 4[email protected], 5[email protected]
Abstract– Characteristics of an integrated antenna are analyzed in terms of the voltage responsivity of a CMOS plasmon detector operating at sub-terahertz frequencies. The voltage responsivity, which is the main factor determining the detector’s performance, shows the ratio between the output voltage level of the detector and the incident signal power.
Nevertheless, the responsivity measurement results in previous studies cannot be easily accepted because the incident power on the detector with the integrated antenna cannot be accurately obtained using the measurement setup. In those studies, simulated characteristics of the differential integrated antenna in the detector were considered for responsivity calculations owing to the difficulty in measuring the performance of the antenna operating at sub-terahertz frequencies. The proposed analysis is based on the previous studies in which the simulation results using the BSIM4 model were identical to the measurement results of the detector without the antenna. The 0.2 THz detector fabricated using TSMC 0.25 μm mixed-signal CMOS technology consists of differential detector cores, pre- amplifiers, main amplifier, bias circuitry, and integrated patch antenna, and is simulated using Cadence Spectre 18. The analysis results show that the compensation of the gain and the return loss of the integrated antenna can represent the calculation of the voltage responsivity as 3.68 times its simulated value.
Keywords—CMOS plasmon detector, effective antenna area, sub-terahertz, voltage responsivity
I. INTRODUCTION
A highly sensitive detector operating in the sub-terahertz frequency band is a key component in the non-destructive see-through imaging systems, such as explosive and toxic detectors, biometric characterization, security systems, and foreign body detectors in foods and materials [1−4]. A CMOS plasmon detector is a promising technology that measures the power of incident signals higher than the operating frequency of the device.
There are two main characteristics that generally show the performance of the detectors: one is the voltage responsivity (Rv) that shows the magnitude of the output voltage depending on the input power of the sub-terahertz signals,
and the other is the noise equivalent power (NEP) that shows the noise level at the detector. High Rv is important in the detector implementation because the NEP of the detector could be reduced by the improvement in the Rv [5].
Accurate measurement of the Rv is indispensable for making performance comparisons with previous studies on sub-terahertz detectors. In a sub-terahertz detector that receives the input signal using an integrated antenna, it is difficult to accurately measure the Rv owing to the uncertainty of the power level at the input node of the detector. Voltage responsivities in the previous studies have been calculated using the product of the power density of the signal source, which is measured with a calorimeter or power meter, and the effective antenna area of the integrated antenna, which is obtained from three-dimensional (3D) electromagnetic wave (EM) simulation results [6−10].
Although the power density of the sub-terahertz signals generally follows Gaussian distribution, the assumption of the evenly incident plane waves on the antenna surface can be accepted in the calculation of the Rv considering that the physical dimensions of the antenna are relatively small compared to the wavelength of the sub-terahertz signal in the air [8, 11, 12]. However, the effective antenna area using the simulation results may not accurately represent the effects of the antenna in the calculation of Rv because the operating frequency of the fabricated antenna is changed by process variations and analysis conditions between simulation and implementation, such as the boundaries and EM field distribution [6, 13, 14]. The performances of a differential antenna are particularly difficult to measure owing to the limitations of the equipment and the difficulty in de- embedding for single-to-differential conversion.
In this study, the effect of the effective antenna area is presented in the calculation of the Rv of the CMOS plasmon detector integrated with a differential antenna. The proposed analysis is based on previous studies wherein the simulation results of the CMOS plasmon detector using the BSIM4 model are similar to the measurement results of the detector without the integrated antenna [15−18]. The comparison analysis between the measurement results of the detector with the integrated antenna and the simulation results without the antenna demonstrates that the Rv of the CMOS detector can be varied by 3.68 times depending on the characteristics of the antenna. The CMOS plasmon detector in the proposed analysis is fabricated using the TSMC 0.25 μm mixed-signal process with one-poly and five-metal a. Corresponding author; [email protected]
Manuscript Received Feb. 28, 2020, Revised Mar. 17, 2020, Accepted Mar. 17, 2020
This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/bync/3.0) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
4 provides the comparison between the measurement and simulation results and the analysis of the effect of the characteristics on the calculation of the Rv. The conclusion is presented in Section 5.
II. ANALYSIS METHODOLOGY A. Voltage responsivity
Responsivity for showing detecting performance is divided into voltage responsivity (Rv) and current responsivity (Ri) depending on the type of the detector output signal. The Rv is used to generally represent the performance in CMOS plasmon detectors because the output of the detectors is in voltage. The output voltage of the detector is at dc level when no modulation technique is used.
Considering the dc offset voltage VDCOFF at the output and the noise power level Pn referred at the input, the Rv of the detector can be expressed as
𝑅𝑣=𝑉𝑜𝑢𝑡− 𝑉𝐷𝐶𝑂𝐹𝐹
𝑃𝑖𝑛− 𝑃𝑛 [V/W], (1) where Pin is the incident signal power at the sub-terahertz frequency and Vout is the dc voltage output of the detector.
When the input signal is modulated with a specific frequency, the changes in the dc outputs can be substituted with the changes in the ac outputs at the modulated frequency. When the Pn can be neglected owing to the small noise level of the detector, (1) can be modified to
𝑅𝑣=𝑉𝑜𝑢𝑡− 𝑉𝐷𝐶𝑂𝐹𝐹
𝑃𝑖𝑛 [V/W]. (2) As the incident power Pin cannot be accurately measured at the input node of the detector with the integrated antenna, Pin
is indirectly calculated using the power density PD of the signal source considering the Friis equation and the effective antenna area Aeff, which is determined by the antenna gain GANT and the wavelength λ of the operating frequency, as presented in [10]
𝑃𝑖𝑛 = 𝑃𝐷∙ 𝐴𝑒𝑓𝑓= 𝑃𝐷∙ 𝜆2𝐺𝐴𝑁𝑇
4𝜋 . (3) The PD in the sub-terahertz band can be measured by the calorimeter or the power meter with a reference antenna at the distance where the detector is positioned from the signal source [11, 19]. The PD with Gaussian distribution can be assumed to that of the plane wave in the far-field condition, and the measured peak PD is generally used in (2) for calculating incident power. The GANT for the calculation of the Aeff can be obtained by using the vector network analyzer or signal transceiver in general; however, the measurement of the GANT of the differential antenna, which is used in the sub-terahertz detector, is not easy to obtain owing to the lack
terahertz band operates in a narrow band owing to the limits of the number and thickness of backend oxide layers (BEOLs), and the frequency characteristics can be easily changed by process variations during fabrication. When the return loss of the antenna is changed by process variations and the incident signal is reflected to a greater extent by the antenna, the calculated Rv at the same measurement output can be increased owing to the decrease in the incident power.
Therefore, the calculation of Rv using the simulation results of the antenna has certain limits to obtain the actual Rv of the detector.
B. Compensation parameter of the characteristics of the integrated antenna
The Rv of the detector should be independent of the characteristics of the antenna because it shows only the characteristics converted from incident sub-terahertz signals to dc output voltages. When the simulation results of the sub- terahertz detector device based on the BSIM4 model are commonly similar to the characteristics of the actual detector device, the difference in the simulation and the measurement are dominantly caused by the characteristics of the antenna.
The compensation parameter α is defined as both the decrease in the PD due to antenna frequency shifting and the decrease in the Aeff due to the small value of Ap. Considering the parameter α, the actual Rv of the CMOS detector can be described with the calculated responsivity Rvc using the simulated data of the antenna as
𝑅𝑣=𝑅𝑣𝑐
𝛼 , (4) where α is a factor that demonstrates the effect of the accuracy of antenna simulation on Rv and an indicator that predicts the performance improvement of the detector by the integrated antenna. The value of α becomes 1 in the ideal case. If antenna characteristics change owing to process variation or the decrease in simulation accuracy, then α is greater than 1. The α cannot be presented with a value lesser than 1 when only the characteristics of the antenna are considered. In the parameter α less than 1, the Rv cannot be calibrated owing to the low simulation accuracy of the detector devices.
III. CIRCUIT IMPLEMENTATION AND ANALYSIS PROCEDURE A. CMOS plasmon detector integrated circuit
The sub-terahertz CMOS plasmon detector is designed at an operating frequency of 0.2 THz as shown in Fig. 1 [8].
The terahertz signals are coupled with a differential patch antenna and transmitted to the gate nodes of the differential detector cores, respectively. The detector cores, in which the
gate bias is set at the virtual ground node of the antenna, convert the incident signal into dc voltages at the drain nodes.
Noise by the leakage at the detector cores can be reduced because the leaked terahertz differential signals in the cores are canceled as a result of being out of phase with the unit- gain preamplifier. The Rv of the detector can be improved because the converted dc voltages are combined in phase to be transmitted to the main amplifier with the voltage gain of 36 dB. The dc offset at the input of the main amplifier can be canceled by the preamplifier with dummy structures, but the dc offset at the output of the main amplifier has remained in the measurement data. The effect of the remaining dc offsets can be neglected in the calculation of the Rv by measuring the difference at the output depending on the input signal presence or absence.
Fig. 2 shows the layout design of the CMOS detector using the TSMC 0.25 μm mixed signal process. The differential integrated antenna has a patch implemented using M5 and PAD layers to avoid the design rules of fabrication. The probe feeding method is realized by using an M4 layer and several via-holes to interconnect the antenna and input nodes of the detector cores. The overall detector including the LDO regulator and current reference circuits is 1410 μm × 1040 μm in size.
B. Performance difference in the integrated antenna between simulation and implementation
The main differences between the simulated and fabricated antennas are the conditions of boundaries and the ground plane. As shown in Fig. 3, the antenna simulation assumes an infinite ground plane (IGP) with the outermost boundary setting as radiation, but the antenna implemented on a chip has a finite ground plane (FGP) using a slotted M1
layer and ground structures connected using vias from M1 to M5 at the outermost part. The differences can be explained by the effect in which the effective antenna area is altered.
The antenna performances depending on the analysis area are simulated by a 3D EM simulator of ANSYS HFSS. The infinite ground plane is generally used in the patch antenna simulation, but the FGP is designed in our simulation for verifying the effect of the analysis area in the integrated antenna. Simulation results of the antennas with the FGP and IGP are shown in Fig. 4. The gain of the antenna with the FGP is 1.2 dBi lesser than that of the antenna with the IGP at zero theta and the beam angle of the antenna with the FGP is also changed with respect to that of the antenna with the IGP. However, the return loss and center frequency in Fig.
4(b) are not seriously altered because the difference at the ground plane does not affect their characteristic impedances.
The simulated reflection coefficient in Fig. 4(b) shows that the integrated antenna operates in the narrow bandwidth.
This characteristic implies that the operating frequency of the antenna can be easily changed by process variations in semiconductor fabrication. For the verification of the Fig. 1. Block diagram of the sub-terahertz CMOS plasmon detector
IC
Fig. 2. Layout of the CMOS sub-terahertz detector IC
(a)
(b)
Fig. 3. Boundaries in the integrated antenna depending on the differences in the ground planes: (a) simulated antenna with radiated
boundaries and an infinite ground plane on M1 metal layer, and (b) fabricated differential antenna implemented by ground layers on M5
and M1 metals
characteristics, the single-ended patch antennas are designed and measured as shown in Fig. 5, instead of the differential antenna using in the CMOS detector. The single-ended antennas are simultaneously fabricated on the same die, but the three antennas are at different positions on the die. The return losses of the antennas are measure by on-wafer probing through a ground-signal-ground input pad, which characteristics are de-embedded by the calibration substrate.
Fig. 5 shows that the center frequencies of the three antennas are shifted down approximately 5 GHz compared to the simulated frequency. The frequency shift does not affect the position on the die, and the shift is caused by the change of the dielectric properties and thicknesses on the BEOLs.
However, as can be seen from Fig. 5, the frequency shift of 5 GHz can lead to the degradation of the incident power of the terahertz signals at the detector owing to the increase in the reflected signals at the antenna. The increase in reflected signal due to the antenna characteristics can affect the Rv by lowering the input power density. Therefore, the analysis shows that Rv can be increased in the calculation using the simulation results of the antenna because of the antenna gain reduction by the FGP and the operating frequency shift by process variations.
IV. ANALYSIS USING MEASUREMENT RESULTS A. Measurement setup
On measuring the detection performance by using the transmitting antenna, the detector receives the signal concentrated or widely scattered according to the beam focusing characteristics of the transmitting antenna.
Moreover, the power of the incident signal of the detector depends on the distance between the detector and the transmitter. Hence, the Friis transmission equation related to Rv is expressed in consideration with the distance of the detector and the characteristics of the transmitting antenna [10].
Measurement setup for the voltage response of the detector including the integrated antenna is shown in Fig. 6.
A gyrotron source is used to transmit terahertz signals to the integrated antenna [11]. The power density of the gyrotron is measured to be 0.7 W/m2 by a calorimeter at the distance in which the detector is located. Using the power density measured by the calorimeter, the Rv can be calculated regardless of the transmission antenna characteristics, as shown in (3). The dc output signal from the detector is measured by an oscilloscope. The effects of all components except the integrated antenna in the Rv of the detector calculation are considered in the measurement.
Fig. 6. Measurement setup for the voltage responsivity of CMOS detectors
Fig. 5. Simulation and measurement results of the single-ended patch antennas simultaneously fabricated in the same process as the
differential antenna for CMOS detectors (a)
(b)
Fig. 4. Simulation results depending on the conditions of the ground plane: (a) antenna gain and (b) magnitude of the S11
B. Analysis of antenna effect on Rv
Fig. 7(a) shows a comparison of the measurement results obtained using the simulated performances of the antenna and the simulation results of the CMOS detector. The circuit simulation of the detector is performed by using Cadence Spectre 18.1 based on BSIM4 device models supported by PDK. The trends of the Rv measured by varying the gate bias of the detector cores are similar in both cases, but the Rv in the measurement results is higher than that in the simulation results, as predicted in the proposed analysis. The measurement results excluding the antenna gain reduction of 1.2 dBi and frequency down-shift of 5 GHz are shown in Fig.
7(b) to verify whether the difference between the simulation and measurement results in Fig. 7(a) is caused by the effects of the integrated antenna. The difference between the two results of Fig. 7 shows that the antenna characteristics have a significant effect on the calculation of Rv. The difference can be expressed by the proposed factor α. The factor α is calculated from the difference between each data point based on the simulation results using least-squares regression [20].
It can be seen that α is 5.26 between the measured Rv
including the antenna simulation results and the simulated Rv. The value of α is decreased from 5.26 to 1.43 between the
modified Rv under the effects of the antenna characteristics and the simulated Rv. Even when compensated with the antenna effects, α does not become 1, implying that other characteristics should be calibrated for the accurate measurement of the Rv. One of these characteristics could be an impedance mismatch between the integrated antenna and detector, which affects the calculation of the Rv in the same manner as due to the frequency shift of the antenna. In addition, the assumption in the proposed analysis that the simulation results of the detector based on the BSIM4 model can describe the measurement results of the detector core may result in imperfect compensation. Nevertheless, the calculated α shows that the measured accuracy of the Rv can be improved by simply compensating the antenna characteristics.
Fig. 8 shows the difference between the simulation and measurement results when full compensation is made using the numerically obtained value of α, i.e., 5.26. Although the trend between the two graphs is similar, it can be seen that the gate bias in which the Rv rapidly increases is shifted and the difference increases at low bias. This result is useful for supporting the results of previous studies that state that CMOS plasmon detectors operate in the sub-threshold region and therefore are required to add device parameters to the simulations that display their behavior in the sub- threshold region [21].
V. CONCLUSION
An analysis of the characteristics of the integrated antenna is proposed for the accurate calculation of Rv in CMOS detectors by comparing the simulation and measurement results. The Rv using the simulated antenna characteristics can differ from the actual value of the detector because the exact characteristics are not obtained in the differential detector IC. The proposed analysis shows that the FGP on the detector and the return loss of the antenna can increase the measurement error in Rv. The decreases in the effective antenna area and incident power density at the inputs of the detector cores cause the calculated Rv to be higher than that obtained in the actual detection performance. The Rv
Fig. 8. Simulation results and the fully calibrated measurement results using the least-square regression
(a)
(b)
Fig. 7. Voltage responsivity of the CMOS detectors at the incident power of –30 dBm depending on the gate bias: simulation results and
(a) measurement results without any compensation and (b) measurement results excluding the effects of the integrated antenna
ACKNOWLEDGMENT
This work was partly supported by the Basic Science Research Program through the NRF funded by the Korea government (MSIT) (No. 2017R1C1B2002285) and IITP grant funded by the Korea government (MSIT) (No. 2018- 0-00711). Chip fabrication and EDA tools were partially supported by the IDEC, Korea.
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Moon Jeong Lee received the B.S degree in electronic engineering from Yeungnam University, Gyeongsan, Korea, in 2020.
Her research interests include RF/analog integrated circuits and sub-terahertz detectors.
Ha Neul Lee received the B.S degree in electronic engineering from Yeungnam University, Gyeongsan, Korea, in 2019.
Her research interests include sub- terahertz imaging systems and high- speed control circuits for detector arrays.
Hyo Jin Lee received the B.S degree in electronic engineering from Yeungnam University, Gyeongsan, Korea, in 2019.
Her research interests include sub- terahertz detectors and millimeter- wave integrated circuits and systems.
Ga Eun Lee received the B.S degree in electronic engineering from Yeungnam University, Gyeongsan, Korea, in 2019.
Her research interests include planar antenna designs, millimeter- wave passive component designs, and sub-terahertz detectors.
Ju Hee Son received the B.S and M.S degrees in electronic engineering from Yeungnam University, Gyeongsan, Korea, in 2018 and 2020, respectively.
Her research interests include planar-type antenna designs and millimeter-wave / sub-terahertz integrated circuits.
Jong Ryul Yang received the B.S degrees in electrical engineering and material science from Ajou University, Suwon, Korea, in 2003, and the Ph. D. degree in electrical engineering from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2009. From 2009 to 2011, he worked with Mixed- Signal Core Design Team, Samsung Electronics, Yongin, Korea. From 2011 to 2016, he was associated with the Advanced Medical Device Research Division, Korea Electrotechnology Research Institute, Ansan, Korea. He was concurrently an Associate Professor in the Department of Energy and Power Conversion Engineering, University of Science and Technology, Ansan, Korea, from Mar. 2012 to Aug. 2016. Since Sep. 2016, he has been an Assistant Professor in the Department of Electronic Engineering, Yeungnam University, Korea. His research interests include RF/millimeter-wave/terahertz circuits and systems, especially miniaturized radar sensors.