Design of a Low-Quiescent-Current Gate-Pole-Dominant

Design of a Low-Quiescent-Current Gate-Pole-Dominant Low-Dropout-Regulator

Joo Eun Bang

¹

, Young Hyun Lim, and Jae Hyouk Choi

^a

Department of Electrical Engineering, Korea Advanced Institute of Science and Technology E-mail: ¹jebang@kaist.ac.kr

Abstract – Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. Low- dropout voltage regulators (LDOs) get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, canceling spurs from other loads, and giving different supply voltages to loads.

Following load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSFET, the topologies of the error amplifier, and the locations of the dominant pole. Analog loads such as voltage- controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-ripple-rejection-ratio (PSRR), high accuracy, and low noise. We present a low- quiescent-current fully-integrated LDO that obtains the desired PSRR.

Keywords—Gate-pole-dominant, High power-supply- rejection-ratio, Low-quiescent-current

I. INTRODUCTION

For the mobile and internet-of-things (IoT) applications, the compact integration and low power dissipation are necessary for chip design. System-on-chip (SoC) that is contained every function in a compact chip become popular since it can remove chip-to-chip path-caused parasitic by removing power and signal delivery between chips.

According this tendency, power management integrated circuits (PMICs) should be fully-integrated and thus more complex strategies are needed when designing these circuits.

As shown in the top of Figure 1, a battery provides charges to the inputs of DC/DC converters and these converters deliver supply voltages to loads containing charges in capacitors (CL,DC/DCs) as the level of desired voltage.

However, these supplies contain large switching ripples by the operation properties of these converters and spurs from other loads sharing the same supply voltage. These problems make the loads which need clean and noise-less supply cannot operate properly. Furthermore, the loads can operate

Battery

DC/DC DC/DC

CPU Camera Display

VCO Memory ADC C

L,DC/DC

C

L,DC/DC Spurs Ripples

Battery

DC/DC

DC/DC CPU

Camera Display VCO Memory

ADC LDO

LDO LDO LDO LDO LDO SoC SoC

Fig. 1. The path of charge delivery from a battery to loads without LDOs (top) and with LDOs (bottom).

optimally in their supply voltage level but DC/DC converters only provide the same voltage level to their loads.

To resolve these problems, low-dropout voltage regulators (LDOs) are added between switching converters and loads as shown in the bottom of Figure 1. Even if the LDOs have lower power efficiency than DC/DC converters due to series connection on current provision path, they can suppress switching ripples from DC/DC converters, reduce spurs from other loads, and provide different supply voltage to the different loads.

As shown in TABLE I, different types of voltage regulators can be used considering the condition of load blocks [1]. Since LDOs can rapidly provide the desired current to the load with less noise, it can be preferred loads that want that kind of properties. The objective of LDOs is that they are seen as an ideal voltage source. It means that the LDO should provide the exact output voltage (VOUT) level to their loads and the level should not be fluctuated by itself or sudden load transition. In other words, it should a. Corresponding author; jaehyouk@kaist.ac.kr

Manuscript Received Apr. 20, 2020, Revised Jun. 11, 2020, Accepted Jun.

19, 2020

This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/bync/3.0) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

TABLE I. Comparison of voltage regulators.

Linear regulator Switching regulator

Efficiency Low High

Noise Low High

Transient response Fast Slow

Step-up voltage No Yes

Step-down voltage Yes Yes

Area Small Large

respond rapidly to the change of load current (IL) and supply of LDO (VIN). LDOs were generally embedded to reduce the noise of DC/DC converters and keep analog loads such as voltage-controlled oscillators (VCOs) and analog-to-digital converters (ADCs) from supply coupling.

In this work, we present a low-quiescent-current (IQ) fully-integrated LDO that obtains the desired power supply ripple rejection ratio (PSRR).

II. PROPOSED LOW DROPOUT REGULATOR A. Stability of LDO by the Location of Dominant Pole

Especially in LDOs, as the IL varies from minimum (IL,min) to maximum (IL,max), the output pole frequency (𝜔_P,OUT) changes dynamically. Satisfying desired PM performance in the worst-case brings lots of degradation of other performances such as lower accuracy, lower PSRR, lower transient responses. Thus, we need more advanced methods than designs that other performance metrics are limited by worst-case of stability. The solution is making the parameters that affect stability adaptively change as the 𝜔P,OUT changes.

The location of the dominant pole is an important consideration. Generally, LDO has two low-frequency poles at the gate (𝜔_P,G) and output node. In the past years, a large off-chip load capacitor (CL) makes LDO be output pole dominant (OPD). As CL size is reduced, some LDOs have gate pole dominant (GPD) property.

Light IL makes GPD LDO more unstable as shown in Figure 2. If load changes, VOUT is compared with the reference voltage (VREF) by error amplifier (EA). EA represents the difference as the change of gate voltage (VG) and PMOS type pass transistor (MP). In [2], the LDO includes the VG sensing block. If VG gets high, the block reduces the bias current of EA. Thus, at IL,min, the LDO can keep stability without the reduction of the BW in heavy load conditions.

Heavy IL makes OPD LDO unstable as shown in Figure 3.

The output resistance of EA (ROUT,EA) and the total capacitance of MP seen from the gate (Cgg) make 𝜔P,G less.

In [3], by dividing EA into a series of a large gain amplifier and a small gain amplifier, the large ROUT,EA can be isolated from the large Cgg. Thus, the LDO can keep stability by just splitting the large resistance and capacitance without extra power consumption to push 𝜔_P,G away.

I

L

V

REF

V

OUT

V

IN

+ EA

C

L

M

P

X X ω

P,G

< ω

P,OUT

ω

P,G

ω

P,OUT

0 ω

P,G

ω

P,OUT

@ I

L,min

ω

P,OUT

@ I

L,max

I

L,min

I

L,max

V

G

Open Loop Gain (dB)

Fig. 2. Stability issue at IL,min in GPD LDO.

I

L

V

REF

V

OUT

V

IN

+ EA

C

L

M

P

X X ω

P,OUT

< ω

P,G

Open Loop Gain (dB)

ω

P,G

ω

P,OUT

0

I

L,min

I

L,max

V

G

R

OUT,EA

C

gg

ω

P,OUT

@ I

L,min

ω

P,OUT

@ I

L,max

ω

P,G

Fig. 3. Stability issue at IL,max in OPD LDO.

B. LDO Target Specification

Analog LDOs are added in a chip for the loads that need noise-less supply such as VCOs and ADCs. In these applications, high PSRR and tight line and load regulation performance are necessary. The target specifications need 50dB of DC open-loop gain (AOL,DC), 10kHz of –3dB bandwidth (BWOL,–3dB), 10μA of IQ, and 10pF of CL. The PSRR condition came from a DC/DC converter that supplies the charge to the LDO with 100mVP-P VIN switching ripple with 50kHz switching frequency. For reducing the amplitude of the ripple to 1mVP-P at VOUT, the target PSRR specification is ≥40dB at 50kHz of frequency. A loading block is VCO that consumes 60mW power and needs 30mA IL,max. To make the static power of the LDO as less than 10% of the load power, dropout voltage from VIN to VOUT (VDO) was limited to less than 200mV.

C. Design of EA

The size of MP should be large as MP with the large W/L ratio can drive target IL,max while operating in the saturation region. The W/L of MP was designed as 3.8mm/30nm. In a decision of the EA structure, we selected a 1-stage NMOS- input PMOS mirror differential to single-ended EA for simplicity as shown in Figure 4. For increasing ROUT,EA, the length of transistors increases. To increase the transconductance of NMOS transistors (gmN,EA) and widen the output dynamic range, the width of transistors increases.

Designed EA has 40dB of DC gain and 12MHz of –3dB bandwidth. If MP is attached to this EA, the gain will increase and bandwidth will be reduced.

D. Design of Load Controller

In Figure 5, a test bench is shown. By changing the bias voltage (VB) of the load controller, we can measure the transient response of the LDO. The structure of the load controller is shown in Figure 6. In this structure, for the load controller keeping desired IL transition (rising and falling) time (Tedge), we should pay attention to the parasitic capacitance (CP) and resistance at the mirror pole since it can limit Tedge due to RC delay at this node. We designed the load controller for performing 100ns of Tedge.

III. RESULTS AND DISCUSSION

The transient response is shown in Figure 7. By using an iprobe, we investigated the open-loop gain and phase of the total system as shown in Figure 8. As we expected, the gain increased and BW–3dB was reduced by attaching MP. By injecting AC signals to the supply, we found the PSR along with frequency as shown in Figure 9. When a DC/DC converter has 100mVP-P switching ripples and 50kHz switching frequency, this LDO can reduce the ripples as less than 1mVP-P at the VOUT.

V

OUT,EA

V

in–

V

in+

V

IN

I

B

=10uA

1.6μ 400n

1.6μ 400n 16μ

400n

16μ 400n

Fig. 4. 1-stage NMOS-input PMOS-mirror EA.

V

REF

V

OUT

V

IN

+ EA

C

L

(=10pF) M

P

iprobe

Load cont. V

B

V

G

3.8m 30n

Fig. 5. Test bench for designed analog LDO.

160μ 200n

640μ 200n

V OUT

V B

C P

Fig. 6. Load controller for designed analog LDO.

IV. CONCLUSION

We presented a low-IQ fully-integrated LDO that obtains the desired PSRR. Moreover, it can respond rapidly to the change of IL and VIN. This LDO can be applied analog loads such as VCOs and ADCs to reduce the noise of DC/DC converters and keep them from supply coupling. As shown in TABLE II, the simulation results satisfied the desired specifications. It can be fully-integrated since the CL of this LDO is only 10pF.

t T

edge

=

100ns

1μs 0.8V

V

OUT

I

L

1mA

32mA

1 2

0.7V

T

R

=24ns T

S

=89ns

ΔV

OUT

= 104mV

T

R

=103ns T

S

= 133ns ΔV

OUT

=

91mV 2 1

Fig. 7. Load transient response of designed analog LDO.

H

OL

(f) @ I

L,min

H

OL

(f) @ I

L,max

H

EA

(f) Open

loop gain (dB) 0

Phase (deg)

A

EA,DC

=40dB A

OL

= 55dB @ I

L,min

A

OL

= 51dB @ I

L,max

f (Hz)

180

BW

–3dB,EA

=12.8MHz

X

f (Hz)

PM=76º PM=80º @ I

L,min

PM=86º @ I

L,max

BW

–3dB,OL

=21.6kHz

@ I

L,min

BW

–3dB,OL

=27.0kHz

@ I

L,max

X

Fig. 8. Transfer functions of designed analog LDO.

PSR (dB)

0

PSR

DC

= –44dB

@ I

L,max

f (Hz)

PSR

50kHz

= –42.5dB @ I

L,max

PSR

50kHz

= –47dB @ I

L,min

PSR

DC

= –53dB

@ I

L,min

50k

Fig. 9. PSRR characteristics of designed analog LDO.

TABLE II. The desired specifications and simulation results.

Perform. metrics Desired Value Simulation results

AOL,DC ≥50dB 51dB @ IL,max

BWOL,–3dB ≥10kHz 21.6kHz @ IL,max

IQ ≤10uA 10uA

CL ≤10pF 10pF

IL,max ≥30mA 32mA

VDO ≤200mV 200mV

Abs(PSR50kHz) ≥40dB 42.5dB @ IL,max

ACKNOWLEDGEMENT

This work was supported in part by the Ministry of Science and ICT, South Korea, through the ITRC Support Program super-vised by IITP under Grant IITP-2017-2017- 0-01635, and in part by the Korea Institute for Advancement of Technology (KIAT) grant funded by Ministry of Trade, Industry and Energy (MOTIE) under Grant N0001883, and EDA tools were supported by IDEC, Korea.

REFERENCES

[1] Maxim Integrated, “Tutorial: Regulator Topologies for Battery-Powered Systems,” Jan. 2001.

[2] C. Zhan and W. H. Ki, “Output-capacitor-free adaptively biased low-dropout regulators,” 2010 IEEE International Conference of Electron Devices and Solid- State Circuits, EDSSC 2010, vol. 57, no. 5, pp. 1017–

1028, 2010.

[3] M. Ho, K. N. Leung, and K. L. Mak, “A low-power fast- transient 90-nm low-dropout regulator with multiple small-gain stages,” IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2466–2475, 2010.

[4] J. Roh, S. Byun, Y. Choi, H. Roh, Y. G. Kim, and J. K.

Kwon, “A 0.9-V 60-μW 1-bit fourth-order delta-sigma modulator with 83-dB dynamic range,” IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 361–370, 2008.

[5] X. Liu et al., “A Modular Hybrid LDO with Fast Load- Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time- Constant Compensation,” Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol.

62, pp. 234–236, 2019.

[6] Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi, “An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique,” IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2675–

2685, 2018.

Joo Eun Bang (S’18) was born in Busan, South Korea, in 1995. She received the B.S. and M.S. degrees in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2018 and 2020, respectively. She is currently pursuing the Ph.D. degree with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea.

Her current research interests include low-power and high-performance analog, mixed-signal, and RF integrated circuits for emerging wireless/wired standards.

Young Hyun Lim (S’14) was born in Gyeongju, Korea, in 1992. He received the B.S. degree in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2015, where he is currently pursuing the combined M.S./Ph.D. degree. He was an Intern with Qualcomm, Inc., San Diego, CA, USA, where he was involved in designing the PLLs in the upcoming TRXs. His research interests include low-power and high-performance analog, mixed signal, and RF integrated circuits for emerging wireless/wired standards.

Mr. Lim was the recipient of the IEEE Student Research Preview (SRP) Award for the outstanding poster at ISSCC in 2019, the Korean Government Scholarship (GPF), and the Honorable Mention and the Bronze Prize at the 24^th and 25^th Samsung Human Tech Paper Award in 2018 and 2019, respectively.

Jae Hyouk Choi (S’06–M’11) was born in Seoul, South Korea, in 1980.

He received the B.S. degree (summa cum laude) in electrical engineering from Seoul National University, Seoul, South Korea, in 2003, and the M.S. and Ph.D. degrees in electrical and computer engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2008 and 2010, respectively.

From 2010 to 2011, he was with Qualcomm, Inc., San Diego, CA, USA, where he was involved in designing multi- standard cellular transceivers. In 2012, he joined the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, and served as a faculty member. Since 2019, he has been an Associate Professor at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea.

Dr. Choi has been a TPC member of the IEEE ISSCC since 2017 and the IEEE ESSCIRC since 2016. He was the country representative of Korea for the ISSCC Far-East region in 2018. His research interests include low-power and

high-performance analog, mixed signal, and RF integrated circuits for emerging wireless/wired standards.