Feasible protection strategy for HVDC system by means of SFCL and passive resonance DC breaker

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The Journal of Engineering

The 14th IET International Conference on AC and DC Power Transmission (ACDC 2018)

Feasible protection strategy for HVDC system by means of SFCL and passive resonance DC breaker

eISSN 2051-3305

Received on 9th October 2018 Accepted on 9th October 2018 E-First on 26th November 2018 doi: 10.1049/joe.2018.9040 www.ietdl.org

Ho-Yun Lee

¹

, Mansoor Asif

¹

, Kyu-Hoon Park

¹

, Bang-Wook Lee

¹

1Department of Electronic Engineering, Hanyang University, Ansan, Republic of Korea E-mail: [email protected]

Abstract: The key obstacle in implementing high-voltage direct current (HVDC) grid, which is considered as the future of power grid, is the absence of effective DC circuit breaker (DCCB). At present, HVDC grid could be based on half-bridge (HB) or full- bridge (FB) voltage source converter (VSC). Among these two converter topologies, FB topology has an advantage of reverse current blocking at a much higher cost compared to HB technology and still requires a DCCB for isolating the faulty line.

Therefore, HB technology is more realistic to implement HVDC grid economically if DC fault current could be controlled more effectively. In this respect, this article suggests feasible fault protection strategy based on superconducting fault current limiter (SFCL) and passive resonance circuit breaker (PRCB) which could be applied effectively to HB system. To evaluate the performance of suggested protection scheme, comparative study of full-bridge modular multilevel converter (FB-MMC) protection was performed. In addition, the process to determine the optimal range for quenching resistance of SFCL was also investigated. Consequently, the authors’ suggested protection scheme has shown remarkably improved fault current limiting and interruption performance compared to FB-MMC protection scheme.

1 Introduction

The high-voltage direct current (HVDC) grid is well known as a viable solution for long-distance bulk power transmission and renewable energy interconnection [1]. However, satisfactory DC current interruption technology has not been developed yet [2].

Voltage source converter (VSC) system which is known as an optimal solution to implement DC grid can be classified into two types, that is the half-bridge (HB) and full-bridge (FB) modular multilevel converters (MMCs) [3]. FB-MMC has a capability to reduce DC fault current artificially by utilising converter-blocking technology. As the converter blocks, the discharging current from sub-module capacitor gives rise to reverse current against fault current, and artificial current zero can be achieved [4]. However, although the FB-MMC could be used to suppress fault current, DCCB is still required to isolate the fault [4, 5].

Meanwhile, HB-MMC is very economical solution compared to FB-MMC, but HB-MMC has no DC fault blocking capability due to the existence of anti-parallel freewheeling diode. Therefore, effective and economical DC fault interruption devices should be devised and commercialised [6].

One of the already suggested economical DC breakers is passive resonance circuit breaker (PRCB), which utilises mechanical scheme to create an artificial zero crossing with parallel LC resonance circuit, but PRCB is only optimised for interrupting small fault currents and its interruption process is too slow to interrupt steeply increasing DC fault current [7]. Therefore, specialised DC interruption technology based on power electronics with ultra-fast switches has been suggested. However, due to its high on-state loss and enormous constructing expenses, the possibility of commercialisation is very low [7, 8].

For this reason, to establish economical protection strategy for HVDC system, the application of superconducting fault current limiter (SFCL) with PRCB on HB-MMC system, which can suppress both transient fault current and energy stress on DCCB, was proposed in this work. If SFCL could effectively suppress the transient fault current as soon as possible, utilising PRCB could be a viable solution.

From our previous work, the feasibility of protection scheme with SFCL and PRCB was reported [9]. In this paper, the economical and efficient protection scheme utilising HB-MMC with PRCB and SFCL was fully investigated to verify feasibility

for both HB-MMC and FB-MMC. To evaluate the suggested protection scheme, test bed model with HB-MMC and FB-MMC with symmetrical monopole structure was designed using MATLAB/Simulink. The comparative studies between the suggested protection strategy for HB-MMC and FB-MMC were performed. To improve interruption capabilities, the study on optimising quenching resistance of SFCL was performed.

2 Simulation model design 2.1 Test bed model

To compare the fault protection scheme between HB-MMC and FB-MMC, a test bed was modelled in MATLAB/Simulink as shown in Fig. 1. 40-level HB-MMC or FB-MMC converter was modelled in the form of point-to-point HVDC system with symmetrical bipolar structure. Reference voltage of DC link is set at 120 kV, and the length of transmission line is 100 km. Pole-to- pole fault is generated at the transmission cable 50 km away from the converter station at 0.1 s, as shown in Fig. 1. After the DC fault in the test bed is initiated, main controller could trip the HB and FB converter within a few microseconds to perform converter protection. By performing these processes, DC fault contribution from sub-module capacitor can be prevented in HB-MMC. In case of FB-MMC, all sub-module capacitors begin to discharge after DC fault, and the discharging current is injected against initial direction of fault current. The specification of system model are summarised in Table 1.

2.2 PRCB model design

Fig. 2 shows a PRCB design comprised of three parallel conducting paths: nominal path which has a mechanical switch, a parallel-coupled commutation path which is composed of inductor and capacitor to create the inverse current, and energy-absorbing path which has a surge arrester for energy absorption. The values of L and C can be determined considering the interruption performance. The value of C was selected as 25 μF, and L was 10 mH. The voltage range of surge arrester was 98–132 kV [7, 8].

After fault detection with 6 μ delay Δt_detect, the mechanical switch in nominal path is opened with 10 ms of opening delay Δt_dccb, and electric arc arises between its contacts. In order to J. Eng., 2019, Vol. 2019 Iss. 16, pp. 767-770

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simulate DC arc phenomena, a modified Cassie–Mayr black-box arc model was adopted. During arc extinction process, current oscillation can occur between the nominal and the commutation paths at the natural frequency (1/LC). If the magnitude of the oscillating current is larger than that of input current, zero crossing occurs and nominal path starts to (see Fig. 3) interrupt the current.

If the voltages between PRCBs reach the (see Table 1) threshold of surge arrester (SA) during arc extinction, the SA would ignite and finally could absorb the remaining energy stress across PRCB.

After these processes, remaining RCB isolates faulty point permanently [7, 8].

2.3 SFCL model design

In the normal state, the state of superconductor moves into resistive state, and the electric field is directly proportional to the current. In other words, it has a high impedance and performs its function in case of all short-circuit cases [10]. The SFCL quenches very quickly within milliseconds to suppress effectively fault current.

The quenching phenomena of SFCL can be expressed as follows:

R_SFCL(t) =

0 (t≤t_q)

R_m(1 −e⁻^t^/^T^C) (t_q≤t) (1) where R_m represents the maximum quenching resistance, and T_c is time constant for the transition to the quenching state. T_c, R_m set up to 0.25 ms and 24 Ω, respectively. The minimum impedance was determined as 0.1 Ω. Transition time was adjusted within 3 ms before the peak current is reached, considering the steep rising time of DC current, and critical current was 2.2 kA [11, 12].

2.4 Operating sequences of HB and FB protection strategy Fig. 4 shows the protection strategy and allocations for FB-MMC with DCCB and suggested HB-MMC with SFCL and PRCB. In case of FB-MMC protection, zero crossing could be formed by converter blocking, and therefore, the application of mechanical CB at converter terminal was considered as a protection equipment. When a fault occurred, controller blocks FB-MMC converter after 6 μs of fault detection delay Δt_detect. Then, MCB trips with 7 ms of operating delay Δt_dccb. During Δt_dccb, FB-MMC converter can operate to make artificial zero crossing. Therefore, as DCCB opens, fault interruption can be achieved [13].

Fig. 1 Test bed model designed by MATLAB/Simulink. Converters are composed of HB or FB-MMC 40 level. The DC fault assumed pole-to-pole fault at middle of the transmission line

Table 1 Summary of HVDC system parameters

Parameters Specifications

VSC HVDC type symmetrical bipolar HB/FB-MMC

AC source voltage 154 kV

number of sub-module per arm 40

equivalent capacitance 10 uF

arm reactance 0.1 mH

transformer power rating 450 MVA

transformer voltage ratio 154 kV / 100 kV

DC cable resistance 0.0133 Ω/km

DC cable inductance 0.8273 mH/km

DC cable capacitance 0.0139 uF/km

length of transmission line 100 km

Fig. 2 Designed passive resonance circuit breaker (PRCB)`

Fig. 3 Resistive superconducting fault current limiter (R-SFCL)

Fig. 4 Protection schemes for MMC DC Systems

(a) Protection scheme for FB-MMC with DC CB, (b) Suggested HB-MMC protection scheme with SFCL and PRCB

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Fig. 4b shows the protection strategy for HB-MMC with SFCL and PRCB. Although the converter-blocking control of HB-MMC cannot make zero crossing, it should be required to protect the IGBT devices. The fault detection delay also was assumed to be 6 μs. When the measured current exceeds critical current of SFCL, it quenches within 3 ms, and fault current can be limited. After the operating delay of PRCB, current interruption is completed during the time of LC resonance. As the SFCL suppressed fault current, the resonance time could be shrunk compared to the case of without SFCL. When the zero crossing is formed, remaining RCB operates and isolates faulty point permanently. The flow chart for each protection strategy is summarised in Fig. 5 [14–17].

3 Simulation result and discussions

In order to confirm the feasibility of suggested protection strategy for HB-MMC, the comparative studies on each protection strategy were performed. In addition, to determine the feasible conditions for HB-MMC protection with SFCL, the additional analyses on optimum quenching resistance for SFCL were determined.

3.1 Analysis of fault current characteristics in FB-MMC system with mechanical circuit breaker

In case of the FB-MMC, converter blocking enables all sub- module capacitor to discharge. Then, the inverse current is injected, and therefore, the fault current correspondingly decreases until zero-crossing [18–22]. However, during this process, current oscillation could occur. Fig. 6 shows the fault current characteristics whether the protection strategy for FB-MMC was applied or not. It was shown that the protection strategy for FB- MMC could reduce the resonance component of FB-MMC fault current but there was no effect on fault current limitations. After converter blocking, zero-crossing formed at 107.2 ms, and then remaining DCCB operates and isolates the faulty point permanently. The measured prospective maximum fault current was 3.12 kA, and total interruption time was 7.2 ms.

3.2 Fault interruption performance of PRCB with SFCL To compare the suggested protection scheme and FB-MMC, quenching resistance Z_SFCL was set to 3 Ω. Without SFCL, 7 kA of maximum fault current was observed, and total interruption time was 23.5 ms as shown in Fig. 7. When SFCL was not applied, PRCB should endure all the fault energy stresses, which causes the increase of size and design cost of PRCB. When the SFCL was applied with 3 Ω of Z_SFCL, the maximum fault current was measured to be 5.32 kA with 20 ms of total interruption time. The red line in Fig. 7 represents waveform of the fault current when 3 Ω of Z_SFCL was applied. Compared to the case of FB-MMC, there is no noticeable improvement. Therefore, additional improvement should be done by determining optimal quench resistance as follows.

3.3 Optimal quenching resistance of SFCL for HB-MMC In order to improve the interruption characteristics of suggested protection strategy, optimal quenching resistance of SFCL was investigated by varying the quenching resistance. Z_SFCL was varied from 3 to 24 Ω with intervals of 3 Ω, and then the fault current was measured with varying Z_SFCL as shown in Fig. 7. The measured peak current, total interruption time, and the current reduction ratio were summarised in Table 2. From the result, it was observed that the peak current and total interruption time were exponentially decreased by increasing Z_SFCL.

In addition, the maximum fault current began to decline at the point of 12 Ω compared to the case of FB-MMC. As the value of Z_SFCL exceeds 18 Ω, the reduction rate of fault current was gradually reduced, and its magnitude began to be saturated with the 2.46 kA of maximum current and 14.1 ms of total interruption time. In comparison with the case ‘without SFCL’, the noticeable enhancements, that is 64.8% current limitation and 40%

interruption time reduction, were observed. In this regard, it was assumed that 21 Ω was the critical value for fault saturation point, which the maximum fault current was almost saturated. In such case, the maximum fault current had been reduced by 0.93 kA compared to FB-MMC. However, the total interruption time was 6.18 ms longer in this case.

From the result, the suggested protection has shown the improved performance compared to FB-MMC protection.

Furthermore, in terms of on-state losses and design cost, it could be more economical and efficient protection scheme. Therefore, the protection scheme utilising HB-MMC with SFCL and PRCB could be considered optimal protection scheme to design the future multiterminal HVDC grid.

Fig. 5 Flow chart for protection scheme

(a) FB-MMC with DC CB, (b) HB-MMC with SFCL and PRCB

Fig. 6 Current characteristics of the protection scheme of FB-MMC system under pole-to-pole fault

Fig. 7 Larger the ZSFCL is, the lower the PRCB total current becomes with the reduction of interruption time

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4 Results

In this paper, compared with the protection by means of FB-MMC with DCCB, which has been known as optimal for DC grid protection, alternative protection scheme using HB-MMC with PRCB and SFCL was suggested. The design of resistive SFCL and PRCB was carried out, and they were allocated at HB-MMC HVDC system. The comparative studies between the suggested protection strategy and FB-MMC with DCCB were performed, and the optimal quenching resistance was investigated. As the quenching resistance of SFCL was increased, the maximum fault current and total interruption time were exponentially decreased to saturation point.

Finally, the optimal range for quenching resistance was determined. The suggested protection scheme using HB-MMC with PRCB and SFCL has shown the improved interruption performance compared to FB-MMC protection. In addition, it could be viable solution to control fault current in HB converter systems for future HVDC grid.

5 References

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Table 2 Percentage Reduction and Total Interruption time in Fault Current for Changing Z_SFCL

Quenching impedance Z_SFCL

Prospective maximum fault

current, kA

Total interruption

time, ms

Percentage reduction, %

NO SFCL 7 23.5 —

3 Ω 5.32 20.4 24.0

6 Ω 4.34 17.5 38.0

9 Ω 3.65 16.4 47.9

12 Ω 3.18 15.8 54.5

15 Ω 2.78 14.7 60.3

18 Ω 2.46 14.1 64.8

21 Ω 2.19 13.3 68.6

24 Ω 2.09 13.1 70.1

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