Introduction
DAC Basics
- DAC architecture
- Resistive DAC
- Capacitive DAC
- Current steering DAC
- Sigma-delta DAC
- DAC specification
- Integral non linearity (INL)
- Differential non linearity (DNL)
- Spurious-free dynamic range (SFDR)
Therefore, the performance of DAC is determined by the ratio of errors and similarity to ideal DAC. There are some other specifications that can stand for the feature of DAC. a) Meaning of INL and (b) two definitions of INL.
Sources of Nonlinearities and Dynamic Errors
- Non-identical current cell design
- Random mismatching errors
- Mismatch classification
- Gradient error
- Code dependent output impedance
- Dynamic errors
- Non-exact timing in the data switches
It uses a common low-voltage DAC core and simple high-voltage protection circuits are added. 22, two high voltage transistors (M1 and M2) are used to prevent the high voltage output from flowing into the current low voltage output node of the DAC (IOUT+ and IOUT-). If the gate of the High Voltage Metal Oxide Semiconductor (HV MOS) transistor has been correctly biased, the sources M1 and M2 (which are equal to the IOUT+ and IOUT- nodes) are protected from the HV MOS drain voltage (VHV+ and VHV-).
Proposed high voltage protection structure DAC is the simplest structure that converts low voltage current control DAC to high voltage current control DAC. Unlike combined structure, the proposed high-voltage protection structure even improves the non-linearity of low-voltage DAC. 30 shows differential output voltage for low voltage mode DAC and proposed high voltage protection mode.
Test chip composed of low voltage DAC core and high voltage protection circuit like you.
Applied Nonlinearity Compensation Method from State-of-the-art
Segmentation
- Binary coded DAC
- Thermometer coded DAC
- Segmented DAC
Simply in the case of a thermo-encoded DAC 1-step transition of the input code, only one current cell of the unit is turned on or off regardless of the previous state. Overlaid 100x MATLAB DNL simulation result with 0.01LSB standard deviation for. a) DAC with thermometer (b) DAC with binary code. Figure 13 (a), (b) shows the DNL results of the thermocoded DAC model and the binary coded DAC model.
These results appear both thermometer coded DAC and binary coded DAC, and both INL distribution is similar. When DAC input is k, thermometer coded DAC's total current output IT(k) is described as below equation. Like the comparison, thermometer-encoded DAC's DNL is the same as each unit cell's current error.
Therefore, the thermometer coded DAC's DNL is the same as the normal distribution, which unit current cell's standard deviation σ.
Random Arrangement
- Centroid
- Quad-quadrant random walk
So, it is able to degenerate the INL due to making the error of the enveloped gradient, which depends on the position. In the central arrangement, the first-order gradient error can be significantly reduced, the cells are symmetrically arranged. This structure degenerates the first-order gradient error in the first-quadrant partition and the higher-order gradient error decay in the second-quadrant partition.
But the second-order error is just accumulated because symmetrical current cells still have the same sign of the second-order gradient error. At the point of the second division axis, the second-order gradient error can again be divided according to the first-order term and the second higher-order term. Degeneration of the first-order gradient error on the second axis also reduces the original second-order gradient error.
Considering the first-order gradient error from the actual 4x4 cells, if the switching sequence is adopted minimizing the accumulation, the INL goes up and down, not leaving the central value.
Dynamic Element Matching
23 is the basic structure of conventional low voltage DAC with differential current output used in high voltage DAC protection. The proposed high voltage protection circuit consists of high voltage transistors, diodes, switches and current sources. The structure that builds the all-current high-voltage transistor DAC usually needs more than thousands of high-voltage transistors.
The proposed high-voltage protection structure reduces the use of the high-voltage transistor by 2, thereby reducing the cost.
Proposed High Voltage Protection
Industrial Application DAC
DAC provides a simple way to apply processed digital signal to analog signal industrial applications. The scale of these current and voltage drive requirements is quite larger than the current and voltage used in conventional digital or analog CMOS integrated circuit (IC). But these high-voltage transistors usually have a complex structure that uses more area than conventional MOSFET.
Because of it, the whole DAC has to be redesigned even though there is a conventional low voltage DAC design. It can reuse existing low-voltage DAC and using much smaller high-voltage transistor than DAC, which replaces the full transistor with high-voltage transistors to meet industrial high-voltage requirements.
Proposed High Voltage Protection Structure
Simple high voltage cascade transistors are not enough to protect conventional low voltage current DAC against high output voltages (VHV+ and VHV-). With n≈N, M1 flows almost full scale current and it operates in saturation region which means that IOUT+ node remains in acceptable low voltage region. With these bleeding current sources and HV MOS, input code independent high voltage protection is guaranteed.
Feedthrough inside low voltage DAC is not that important, because all signals inside low voltage core are smaller than the operation voltage of conventional transistor and feedthrough voltage does not differ so much with the operation voltage of conventional transistor like clock feedthrough. But signal at high voltage node is usually much larger than the operation voltage of conventional transistor. Forward voltage from high voltage node can also be much larger than the working voltage of conventional transistor.
Advantage of Proposed Structure
- Simplest way to convert low voltage DAC to high voltage DAC
- Nonlinearity compensation by proposed structure
- Power efficiency
Proposed high voltage protection DAC with (a) only HV MOS and (b) additional bleed current source. voltage DAC and high voltage driving amplifier use high voltage transistor only on driving amplifier. Therefore, it is much cheaper than previous structure and easy to convert existing low voltage DAC to high voltage DAC. In addition to the reduction of expensive high-voltage transistors, the proposed structure does not need additional power by using both DAC and driving amplifier.
As explained in the previous chapter, the current drive DAC has internal nonlinearity dependent on the code from the finite output impedance of the current cell. The current of the unit cell is Io, the output impedance of each cell is Zo, the total number of current unit cell is N, and the data input is n (-N ≤ n ≤ N). The DAC operating at low voltage has a small possible output swing range because reducing the voltage drop in the current cell is difficult.
Power efficiency is the power consumed in the load out of the total power and the output swing range is the possible output swing from the supplied voltage.
Test Result
To increase resolution, current steering DAC needs to add a lot of transistor and need a lot of area. Fundamental structure of proposed DAC is simply combination of ∑Δ modulator and conventional current steering DAC. However, the proposed structure still has fast speed because recent current sending DAC is very fast.
A recent high-speed current control DAC operating over GS/s makes the proposed DAC fast enough. Although the proposed structure has lower resolution than ∑Δ DAC, it is faster than them and more accurate than conventional current control DAC. The latest control DAC becomes fast enough to cover more than GHz range with the development of technologies.
Tai-Haur, "A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection," Solid-State Circuits, IEEE Journal of, vol.
Current Steering DAC with Resolution Improving Sigma-delta modulation
Sigma-delta Modulation Noise Shaping
- Sigma-delta modulation
- Combining between current steering DAC and sigma-delta modulator
From another point of view, ∑Δ DAC has high resolution, but its speed is limited by oversampling.
Proposed Current Steering DAC with Resolution Improving Sigma-delta Modulator
- Proposed resolution improving current steering DAC basics
- Implemented structure of resolution improving sigma-delta modulation
In the actual implementation of the proposed DAC, not all input data (N bit), but enhanced LSB data (N-M bit) need to be modulated. Data with only enhanced resolution (N-M bit) suffers from quantization and must be expressed using the current cell with the upper bit. The Sigma-delta modulator used for testing the proposed structure is the second order modulator in Figure 2.
Advantage of Proposed structure
- Resolution increasing
- Multi resolution possibility
It can still work as high speed DAC if ∑Δ modulator is turned off because MSB input is not modulated by ∑Δ modulator. On the other hand, proposed DAC can be used as high resolution DAC with ∑Δ modulator. Like this way, proposed DAC is easily converted into high resolution mode and high speed mode.
Test result
The high voltage protection circuit is designed as described in Chapter 3. The low voltage DAC core includes all the functions explained in Chapter 4. Included functions are ∑Δ modulator, Q2 random walk, DEM and segmentation. High voltage protection circuit uses LDMOS, whose operating drain voltage is 40V. a) Layout of the test chip (b) Photo of the test chip. There are not only analog power blocks, but also performance-enhancing digital blocks and high-voltage protection circuits.
Low voltage mode is tested at 1.8V supply voltage and high voltage mode is tested at 12V supply voltage. One is high-voltage alternating current DAC for industrial use, and the other is resolution improvement by sigma-delta modulation second state-of-the-art linearity compensation method. But conventional CMOS process DAC cannot handle high voltage (above 5V) because this high voltage exceeds the conventional CMOS operating voltage.
Hofmann, "120 V High Voltage DAC Array for Tunable Antenna in Communication System," in Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, 2014, p.
Test Chip Implementation
Chip implementation
Because MSB is dominant for DAC performance, RRBS DEM is applied to two MSB side segments.
Test result
Chip implementation
Test chip has 12-bit current DAC and improves resolution by 2-bit with ∑Δ modulator noise shaping. MSB segment is designed as binary coded DAC and other two segments connected with DEM and Q2 random walk.
Test result
By applying both methods, DAC can be used in different applications that require different operating voltages and resolutions. Tai-Haur, "Nyquist-Rate Current Steering Digital-to-Analog Converters with Arbitrary Multiple Data-Weighted Averaging Technique and QN Rotated Walk Switching Scheme," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. Galton, "Spectral shaping of circuit errors in digital-to-analog converters," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol.
Hamilton, "Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC," in TENCON Spring Conference, 2013 IEEE, 2013, p. Po-Chiun, "Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Controlled DACs," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. Katakwar, "Placement-Based Nonlinearity Reduction Technique for Differential Current-Controlled DAC," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.
Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol.
Conclusion
