P-38: Low-power High-slew-rate CMOS Buffer Amplifier for Flat Panel Display Drivers

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P-38 / S.-K. Kim

P-38: Low-power High-slew-rate CMOS Buffer Amplifier for Flat Panel Display Drivers

Sang-Kyung Kim, Young-Suk Son, Yong-Joon Jeon, Jin-Yong Jeon, Geon-Ho Lee, and Gyu-Hyeong Cho

Dept. of Electrical Engineering and Computer Science, Div. of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea

Abstract

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed for voltage buffer in flat panel displays. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V/μs for a load capacitance of 1 nF almost independently of static currents as low as 1 μA, this buffer amplifier is promising for column driver ICs of flat panel displays.

1. Introduction

The columns of flat display panels using liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs) are heavily capacitive electronically. Therefore, the active-matrix (AM) and passive-matrix (PM) LCDs, as well as voltage-driven AMOLEDs and PMOLEDs, require voltage buffer amplifiers in the column drivers. As the display resolution increases, the load capacitance of one buffer increases, whereas the required settling time decreases. In addition, hundreds of buffer amplifiers are integrated into one driver IC. Consequently, a high-slew-rate buffer amplifier with low static power consumption is indispensable.

Although the class-AB folded-cascode operational amplifier described in [1] has been used widely as a buffer amplifier in the column driver, it only has a slew rate proportional to the input bias current. To increase the slew rate without wasting static current, several buffer amplifiers for the LCD column drivers have used additional class B- or C-type slew detectors [2-5]. A historic paper [6] introduced an adaptive biasing technique that added the copied version of the output driving current to the tail current of the differential input during the driving transient period.

We present a newly developed buffer amplifier suitable for the flat panel driver ICs. The amplifier has a very high slew rate while consumes a very small static bias current. The static current and the slew rate can be designed independently, and several control parameters for the slew rate are given. Through fabrication and experiments, we verified the operation and the superior performance of the proposed buffer amplifier.

2. Proposed circuit and operation

Figure 1 shows the schematic of the proposed buffer amplifier.

The circuit is composed of two parts. The upper part has an NMOS-input stage that drives the output PMOS MP for the sourcing current, and the lower part has a PMOS-input stage that drives the output NMOS MN for the sinking current. Each part has two positive-feedback loops and includes one negative- feedback loop. For the upper part, the positive-feedback loop1 comprises M5-M10 and the positive-feedback loop2 includes M1

and M11 merged into loop1. Loop1 influences the static state, whereas loop2 is responsible for the high-slew-rate dynamic drive.

In the static state, since the input voltage and the output voltage are the same, the positive-feedback loop2 of each part balances the negative-feedback loop comprised of M9(A)-M11(A)-M2(A)- M8(A). Since the highest-impedance node of the total circuit is the output node, the load capacitance and resistance in the unity- gain negative-feedback loop perform the frequency compensation.

On the other hand, IM7(A) = IM4(A) + IM10(A) and IM7(A) = IM8(A) is in loop1, therefore the current IM7(A) can be expressed as

,

1 1

1 ) ( 4 ) (

7 ⎟⎟⎠

⎜⎜ ⎞

⎝

⎛

× −

=I k

I_M _A _M _A (1)

where k1 is the size ratio of M9(A) and M10(A), and it should satisfy 0 < k₁ < 1. Then, the output current in the static state is calculated as

Figure 1. Proposed buffer amplifier

Vdd

Vin+ Vout

vbp2

vbn2 vbp1

vbn1 M1

M1A M2

M3

M4

M5 M6

M7 M8

M10 M9

M11

MP

M2A M3A

M4A

M5A M6A

M7A M8A

M10A M9A M11A

MN

CL RL (a)

(a*k1) (a*k2)

IM4

Iout (b) (b) (b*k3)

Vin- IM3

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P-38 / S.-K. Kim

I_out,_static =

(

⁰^.⁵×

(

I_M3(_A)+k2×I_M7(_A)

)

+I_M7(_A)

)

×k3^,⁽²⁾

where k₂ is the size ratio of M9(A) and M11(A), and k₃ is the size ratio of M5(A) and MP(N). The Early effect and mismatches of transistors are neglected, and IM4 and IM4A are assumed to be the same in this analysis. Note that by letting the constant current sources IM3(A) and IM4(A) be very small, e.g. tens of nanoampere, the amplifier can be biased in the weak inversion region, hence can be designed to consume a very low static current and to have higher gain.

When there is a voltage difference in the differential input, a very high current can flow through either MP or MN, depending on the polarity of the input differential signal, by the operation of the positive-feedback loop2. That is, loop2 of the upper part operates when Vin+ > Vin-, whereas loop2 of the lower part works when Vin+ < Vin-. The small currents IM3(A) and IM4(A) can be neglected in this dynamic state. For the case of k₂≥1, the output driving current increases until M5(A) and M6(A) enter the triode region, as long as a large differential input exists. For the case of Vin+ < Vin-, the maximum sinking current is calculated as follows:

, ) 2

2 (

1 2

5 , 7

max ,

7 triM A thn

A M ox n A

M vbn V V

L C W

I ⎟ × − −

⎠

⎜ ⎞

⎝

= μ ⎛ ⁽³⁾

,

1 ₇ _max

1 2 3 5 3 max

, M A M A,

nking

si I

k k k I k

I ⎟⎟⎠×

⎜⎜ ⎞

⎝

⎛ +

×

=

×

= ⁽⁴⁾

where Vtri,M5A is the drain-source voltage of M5A held in the triode region, and Vthn is the threshold voltage of NMOS. The Early effect and mismatches of transistors are neglected again.

The parameters that control the maximum sourcing or sinking current are vbp(n)2, the size of M7(A), and the size ratios of k2

and k3. It should be noted that the preceding two parameters can be designed independently of the static bias current, and the output current is still controlled even when k2≥1 [6].

3. Design and Experiments

Table 1 summarizes the design parameters of the buffer. We manufactured the proposed buffer amplifier using a 0.35 μm CMOS process. The designed amplifier was biased to consume a current of 1 μA from the 3.3 V single supply. Figure 2 shows the

M1, M2, M3 20 um M1A, M2A, M3A 60 um

M4 5 um M4A 15 um

M5, M6 30 um M5A, M6A 10 um

M7, M8 60 um M7A, M8A 20 um

M9 20 um M9A 60 um

M10 k1*20 um M10A k1*60 um

M11 k2*20 um M11A k2*60 um

MP 150 um MN 50 um

L = 0.5um, k₁= 0.5, k₂= 1 or 2 Vdd = 3.3 V

Vd (V)

-1.0 -0.5 0.0 0.5 1.0

Output current (mA)

-10 -5 0 5 10

vbn2=0.85, k2=1 vbn2=1.0, k2=1

vbn2=0.75, k2=1

vbn2=1.0, k2=2

vbp2=2.2, k2=1 vbp2=2.3, k2=1 vbp2=2.4, k2=1 vbp2=2.2, k2=2

output driving currents according to the swept dc input differential voltage to support the analysis shown with Eqs. (3) and (4).

The fabricated buffers showed the offset voltages less than 10 mV in the entire operating region. Figure 3 shows the slewing characteristics. Figure 3(a) is for a load capacitance of only 1 nF, and Figure 2(b) is for a load of an LCD panel model [7].

Figure 4 verifies Eqs. (3) and (4) by showing the variation of the slew rate according to the parameters k2 and vbn(p)2.

Figure 5 compares the performance of the designed buffer amplifier with those of other buffers for LCD drivers [2-5]. In this figure, the comparison index was defined as the ratio of the slew rate to static power consumption. The performance of our buffer was measured under the conditions of k2 = 1, vbn2 = 1.0 V, and vbp2 = 2.2 V, while the slew rates reported in other works were converted for a load capacitance of 1 nF. Figure 5 shows that the buffer amplifier designed in this work has a superior performance compared with other buffers, although it is not at its best.

Furthermore, the buffer amplifier in this work requires a small silicon area due to its simple configuration and the dispensability of additional compensation capacitors, and is thus more attractive for driver ICs of flat panel displays.

1nF A

B A

B

(a)

Table 1. Design parameters of fabricated buffer amplifier

Figure 2. Current driving characteristics

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P-38 / S.-K. Kim

68pF 33pF 68pF 33pF

300Ω 6.8kΩ 6.8kΩ 6.8kΩ B

A

A B

(b)

vbn(p)2 (V)

0.6 0.8 1.0 1.2 1.8 2.0 2.2 2.4 2.6

slew rate (V/us)

0 5 10 15 20 25

4. Conclusion

We suggested, fabricated, and measured a new high-slew-rate buffer amplifier that has great potential for applications in flat

[5] [4] [3] [2] this work

slew rate / static power consumption

0.001 0.01 0.1 1 10

panel displays. The amplifier has a large current-driving capability by employing well-controlled positive current feedback loops and has control parameters for the maximum driving current.

5. References

[1] R. Hogervorst, J. P. Tero, G. H. Eschaizier, and J. H.

Huisjing, “A Compact Power-Efficient 3 V CMOS Rail-to- Rail Input/Output Operational Amplifier for VLSI Cell Libraries”, IEEE J. Solid-State Circuits, Vol. 29, No. 12, pp.

1505-1513, 1994.

[2] T. Itakura, H. Minamizaki, T. Saito, and T. Kuroda, “A 402- Output TFT-LCD Driver IC with Power Control Based on the Number of Colors Selected”, IEEE J. Solid-State Circuits, Vol. 38, No. 3, pp. 503-510, 2003.

[3] C-W. Lu and K-J. Hsu, “A High-Speed Low-Power Rail-to- Rail Column Driver for AMLCD Application”, IEEE J.

Solid-State Circuits, Vol. 39, No. 8, pp. 1313-1320, 2004.

[4] P-C. Yu and J-C. Wu, “A Class-B Output Buffer for Flat- Panel-Display Column Driver”, IEEE J. Solid-State Circuits, Vol. 34, No. 1, pp. 116-119, 1994.

[5] C-W. Lu, “High-Speed Driving Scheme and Compact High- Speed Low-Power Rail-to-Rail Class-B Buffer Amplifier for LCD Applications”, IEEE J. Solid-State Circuits, Vol. 39, No. 11, pp. 1938-1947, 2004.

[6] M. G. DeGrauwe, J. Rijmenants, E. A. Vittoz, and H. J.

DeMan, “Adaptive Biasing CMOS Amplifiers”, IEEE J.

Solid-State Circuits, Vol. 17, No. 3, pp. 522-528, 1982.

[7] S-J. Kim, Y-C. Sung, and O-K. Kwon, “Pre-Emphasis Driving Method for Large Size and high Resolution TFT- LCDs”, in SID Int. Sym. Digest of Tech. Papers, Vol.

XXXIV, pp. 1354-1357, May 2003.

Figure 4. Variation of slew rate for load capacitance of 1 nF

▼ falling slew rate for k2=2 ▲ rising slew rate for k2=2

● falling slew rate for k₂=1 ■ rising slew rate for k₂=1 Figure 3. Square responses of the buffer amplifier (k2 = 1, vbn2 = 1.0 V, and vbp2 = 2.2 V)

(a) for load capacitance of 1 nF (b) for load of modelled LCD column[7]

Figure 5. Comparison of performance for the load

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