Tunnel Junction-Embedded Field-Effect Transistor for Negative Differential Resistance and Its Multi-

Introduction

Negative Differential Resistance (NDR) Devices

Our Approach

In this thesis, I propose novel single and multiple NDR devices with ultra-high PVCR above 106 at 1V, based on the embedded tunnel junction effect transistor, which suppresses the valley current with the off-leakage transistor level. In many NDR devices, band-to-band tunneling (BTBT) at the tunnel junction provides the first peak, and the second peak and trough are created by the diode current being suppressed by the off-state transistor. Therefore, the integrated transistor has a primary role for peak and valley currents and ultra-high PVCR.

By using a silicon nanowire (SNW) gate all around (GAA) transistor, which has a high gate control capability, the transistor capability is improved. These multiple characteristics of NDR can be controlled by the doping concentration of the tunnel diode and the threshold voltage of the embedded transistors. In the latch circuit for MVL/MVP applications, a compact design with the smallest cell size is feasible by introducing a three-state voltage transfer circuit.

Thesis Overview

Based on these considerations, JL SNW FETs can be a breakthrough in the problems of conventional CMOS devices. Therefore, the effect of substrate-related parameters can be neglected in the VJL SNW FET with a source-bottom structure, and the effect of Rs dominates. The output characteristics of transistors in the RF range can certainly be affected by Rsub and Csub.

These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be more than 104 at a low operating voltage of 0.5 V in a single peak and valley current. Single or multiple NDR curves can be observed by adjusting the threshold voltage of NW transistor.

In the case of tunnel connections, the higher peak current can be expected due to BTBT at lower source bias (Fig. Single NDR curve with ultra-high PVCR above 104 can be obtained at low supply voltage of 0.5 V. 2-24(a) ) as the valley current can is completely suppressed due to the depletion under the higher gate bias.

At a low gate bias (on state) of the NW transistor, the source voltage can be transferred to the p region of the tunnel diode. The multiple NDR characteristics can be controlled by design parameters such as doping concentration, junction area of the diode and threshold voltage of the NW transistor. By applying a high gate voltage for a high peak current, a higher (2nd) PVCR can be obtained, as shown in Figure 2.

In this structure, the floating potential of the p region can be affected by both the drain and gate biases simultaneously. In the off state (bottom) case, the high channel potential barrier of MOSFET inhibits the flow of electrons, so that the device current can be suppressed at the MOSFET off current level. The multiple NDR characteristics can be controlled by design parameters such as the doping concentration of the tunnel junction and the gate work function (WF) of the MOSFETs embedded in the tunnel junction, as shown in Figure 2.

The 1st and 2nd NDR can be controlled using design parameters of pn tunnel junction and MOSFET respectively. In addition, the 5-state memory can be obtained with 4 transistors in a complementary NDR-based latch circuit.

Figure 2-1. Progression of device structure

NDR Device based on Nano-Wire Junctionless Field-Effect-Transistor and PN Tunnel

Vertical Junctionless (VJL) Silicon Nanowire (SNW) Field-Effect-Transistor

Device Structure and Operation Principle
DC Characteristics
RF Characteristics

PN Tunnel-Junction

NDR Characteristic

A tunnel diode or Esaki diode is a type of semiconductor diode capable of very fast operation using the quantum tunneling phenomenon. A heavily doped pn junction makes a very small depletion region, and band-to-band tunneling (BTBT) occurs with little forward bias through these depletion regions. Moreover, tunnel diodes exhibit negative differential resistance region, and this non-monotonic behavior has the potential for multifunctional operation.

In the steady state region, the conduction band of the n-type doped region is below the valence band of the p-type doped region with very narrow gap width. When a small forward bias is applied, electrons are channeled from the conduction band of the n-type region to the valance band of the p-type region and holes tunnel in reverse. When the applied voltage is further increased, each band faces the forbidden energy bandgap and the BTBT current decreases forming the peak current and the NDR region.

However, through the traps in the energy band gap, the field-dependent trap-assisted tunneling makes the valley current [Fig. As the voltage is increased further, the tunnel diode begins to function as a normal diode, where electrons travel by diffusion rather than by tunneling [Fig. Energy band diagram of the tunnel diode under different current flow mechanisms: (a) band-to-band tunneling, (b) trap-assisted tunneling, and (c) diffusion.

For the leakage current behavior through a forbidden energy band gap, conventional field-dependent TAT model is used [53].

Figure 2-21 shows conventional 2-terminal Esaki tunnel diode simulation results which reproduce NDR with realistic valley current owing to TAT with PVCR below 10

Proposed NDR Device

Single NDR Characteristics
Multiple NDR Characteristics
Comparison between Carrier Injection Mechanisms

If we increase the gate bias faster than source bias, the potential barrier for holes increases and thus NDR can be obtained with ultra-low valley current. However, after the tunnel junction is obtained by degenerate doping, both the increased peak current and lower voltage operation can be achieved due to the additional carrier injection from the tunnel junction at a lower bias condition. 2-25, single NDR curves can be obtained with ultra-high PVCR over 104 at low supply voltage of 0.5 V by suppressing valley current from turn-off NW transistor (VG from 0 to 1 V) with lower gate function (WF) = 4 .5 eV).

It should be noted that the single peaks result from the BTBT mechanism of the tunnel diode as the peak current levels can be increased by increasing the doping concentration. Higher PVCR above 105 can only be expected by considering peak current enhancement (eg lower bandgap materials) as valley current can always be suppressed as NW transistor out current at lower voltage of operation below 0.5 V. In our simulation work, the complementary pNDR device can also be implemented based on the p-MOSFET with the tunnel diode, which is designed with n+ and p+ doping concentrations of 5×1020cm-3 and a typical area junction contact of 100×100nm2. a) Device structure and circuit symbol of the proposed nNDR device (n-type NDR) combining pn-tunnel diode with n-MOSFET (b) energy band diagrams with carrier (electron) injection mechanism in the state (e upper) and off-state (low) of the n-MOSFET.

When the combined tunnel junction MOSFET works in the on state (upper), it supplies the channel electrons to the tunnel diode and then the first NDR curve can be obtained by BTBT, TAT and diffusion as in a normal tunnel diode. Therefore, we can control each 1st and 2nd NDR by using design parameters of p-n tunnel junction and MOSFET respectively. Based on NDR device, static random access memory (SRAM) can be realized with smaller cell size compared to conventional cells.

As shown in the solid and dashed simulation results, the delay can be further reduced below 5 ns by increasing the peak currents up to 60 μA. Thus, it can be expected that the 5-state MVL/MVM operation speed can be further increased by developing high peak current density tunnel junction technology. In this thesis, I proposed the novel NDR device with ultra-high PVCR above 106 that has complementary single and multiple NDR characteristics at 1 V operation based on VJL SNW embedded tunnel junction FET structure and embedded tunnel junction MOSFET structure pn.

In the multiple NDR characteristics, the pn tunnel junction controls the 1st NDR and transistors control the 2nd NDR characteristics.

Figure 2-23 illustrates the operation principle of different doping concentration of pn junction by the energy band diagrams

NDR Device based on Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)

Device Structure and Operation Principle

Figure 1(a) shows the 2D cross-sectional view and circuit symbol of the proposed n-type NDR (nNDR) device based on the simple n-MOSFET structure with a degenerate doped pn tunnel junction at the drain side.

Circuit Configuration

Three-state voltage transfer circuit (a) and curves (b), and its corresponding I-V characteristics of nMOS and pMOS (c). It allows multiple NDR features in a complementary manner for practical MVL and MVM applications with a compact circuit design. CMOS, nNDR and pNDR latch circuit configuration for multiple complementary NDR based on three-state VG transfer during a single sweep of the VOUT terminal.

These simulated doping-dependent peak current values were compared with the experimental data of Si tunnel transitions based on BTBT. In the mimetic IV curves there are two stable (black circle) and one unstable (white) state. Various single and multiple NDR characteristics were obtained with different device configurations between pn diode and transistor.

These NDR characteristics were investigated by analyzing each current component (BTBT, TAT and diffusion) according to the device design parameters. In multi-value memory applications, I will develop the embedded latch circuit and make compact design SRAM circuit. To develop the latch circuit in SRAM, the read and write method must be completed.

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