In this thesis, frequency synthesizers with ultra-low jitter in mmW band based on cascade architecture are presented. In the first stage, the CP PLL operating at GHz band frequencies generated low-jitter output signals due to the high-Q VCO. In the second stage, the ILFM operating at mmW band frequencies has a wide injection bandwidth so that the jitter performance of the mmW band output signals is determined by the PLL in the GHz range.
The proposed CP PLL-based ultra-low-jitter mmW-band frequency synthesizer fabricated in 65-nm CMOS technology generated output signals from GHz-band frequencies to mmW-band frequencies, achieving RMS jitter of 206 fs and IPN -31 dBc. However, due to the large contribution of the in-band phase noise of the PFD and CP to the CP PLL, it was difficult to achieve extremely low in-band phase noise at this first stage. Second, to further improve the in-band phase noise, a digital SSPLL-based mmW band frequency synthesizer is presented.
In the first stage, a digital SSPLL operating at GHz band frequencies produced ultra-low jitter output signals due to the operation of subsampling and a high-Q GHz VCO. The proposed mmW-band ultra-low-jitter frequency synthesizer fabricated in 65-nm CMOS technology produced output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 77 fs and an IPN of –40 dBc.
Introduction
Digital PLLs require high-performance ADCs to reduce quantization noise, which at the same time have high sampling rates, fine resolutions and full coverage of the input voltage signal, but they inevitably require higher power consumption and larger silicon area. To solve this dilemma of quantization noise problem in traditional digital SSPLLs, a new voltage domain quantization technique is presented using the proposed OSVC, which requires only a small amount of silicon area and power while minimizing the quantization error. The design of the mmW band frequency synthesizer based on a CP PLL and the limitations of CP PLL are presented in Chapter 3.
In Chapter 4, the design of the mmW-band frequency synthesizer based on a digital SSPLL is presented.
Practical problems of single-stage frequency synthesizers
Single-stage ILFMs
Single-stage SSPLLs
Design of the mmW-band frequency synthesizer based on a CP PLL
- Concept
- Advantages
- Implementation
- Fractional-N CP PLL
- mmW-band ILFM
- Limitation of the CP PLL
Although many ILFMs are needed to cover different bands, any frequency deviations of the ILFMs can be corrected by a single FTL [7], thus avoiding the phase noise degradation of all signals in multiple bands. It is possible to save the energy consumption of the signal distributions by transmitting a first phase signal of the GHz band PLL to all channels worldwide and then delivering a signal locally using a mmW band ILFM in each channel. This architecture can also reduce the imbalance of the quadrature signals as the ILFM can generate the quadrature signals just before each channel.
The doubled reference frequency allows the division number of the divider to be halved, which can suppress the degradation in the in-band noise caused by building blocks such as a PFD, a CP and a divider. In the passive loop filter of the CP PLL, the characteristics are mainly determined by C1, C2 and R2. In the layout, an additional RC-RC filter was placed just before the control voltage node of the VCO to suppress high-frequency noise via the long metal line from the loop filter to the control voltage.
This RC-RC filter, consisting of R3, C3, R4 and C4, also provides additional filtering to suppress the reference spurt and quantization noise of the DSM and can be used to calibrate the phase margin of the loop. To generate the quadrature signal, the differential outputs of the CP PLL were used with the divide-by-2 divider. The quadrature injection signals (INJ_I±/Q±) are generated by the pulse generators (PGs) and delivered to the quadrature VCO (QVCO) in mmW band.
An FTL was used for frequency operation calibration of the QVCO while consuming less than 900 μW [16]. Since the extra jitter from ILFM can be reduced to a negligible level, designing a GHz-band CP PLL with ultra-low jitter is the most critical to generate mmW-band signals that have ultra-low output jitter. However, the CP PLL has a limitation to reduce the phase noise from the PLL's components, such as PFD and CP, which are dominant components in general.
Also, since it can achieve a sufficiently wider inclusion range than a single-stage, mmW-band SSPLL, stable operation in this GHz-band SSPLL can be ensured.
Design of the mmW-band frequency synthesizer based on a digital SSPLL
- Conventional digital SSPLLs using a multi-bit ADC
- The proposed digital SSPLL using the optimally-spaced voltage comparators (OSVC)
- The RMS jitters of the multi-bit ADC-based SSPLL and the OSVC-based SSPLL
- Implementation
- Cascaded Architecture
- OSVC and V TH -controller
- Loop-gain optimizer
The OSVC has an optimal distance between the VRTHRs of the one-bit VCs by optimizing VRTHRs. By co-optimizing the distance between VRTHRs and the value of K, the amount of quantization noise can be significantly minimized by the low-power, low-complexity OSVC. The RMS jitters of the multi-bit ADC-based SSPLL and the OSVC-based SSPLL.
In this simulation, the RMS jitter of a typical digital SSPLL using an M-bit ADC is shown in Fig. From this, the value of M required by a digital SSPLL using ADC for the same RMS jitter performance as a digital SSPLL using OSVC is estimated. The normalized RMS jitter of the digital SSPLL using OSVC was about 1.06, which means that the degradation was 6% compared to the ideal SSPLL without quantization noise.
Since the resolution was not good enough to quantify the quantization noise in the ADC, the RMS jitter of the digital SSPLL using the M-bit ADC was almost unchanged until the value of M changed from two to six. As the value of M was changed from six to nine, the RMS jitter of the SSPLL was gradually reduced, since the ADC could quantize the quantization noise more accurately. Then, when the value of M was greater than nine, the RMS jitter was almost unchanged again due to the sufficient resolution of the ADC.
DLF consists of the proportional path gain, KP, and the integral (I) path gain, KI. To prevent the problem of false locking of the SSPLL, a simple FLL can be used in the background [5]. The VC of the OSVC was implemented based on regenerative comparators with double-tail topology [30].
Then, the transient behavior of the digital SSPLL was performed using OSVC by varying the value of (VROS,HR – VROS,MR) and monitoring the VRTH+R result. According to the DRMR autocorrelation value, the KRPR value is controlled accordingly. Thus, the optimum value of the loop gain and bandwidth of the digital SSPLL can be maintained by controlling the value of KRPR in the DLF in the background.
Experimental Results
This work achieved the lowest values of RMS jitter, IPN and FoMRJIT among mmW-band frequency synthesizers. Hybrid PLL Fully digital PLL Fully digital PLL GHz-PLL + ILFM chain Type Fractional-N Fractional-N Fractional-N Fractional-N Fractional-N.
The measured RMS jitters of the OSVC-based digital SSPLL, when the output frequency of the SSPLL swung from 3.3 to 4.1 GHz as shown in Fig. The digital SSPLL achieved ultra-low jitter maintaining less than 80 fs over the entire output frequencies. This is because the VRTHR controller and the loop gain optimizer controlled the values of VRTHRs of the OSVC and K of the loop in the background.
The phase noises at 3.8 and 28.5 GHz are measured on the blue line and on the red line, respectively. Due to the wide injection bandwidth of more than 200 MHz of the mmW ILFM band, the phase noise of the mmW ILFM band followed the phase noise of the SSPLL with the theoretical value, 20log (NR2R). As shown in Table 2, the proposed digital SSPLL achieved the lowest RMS jitter of 72 fs and FoMRJITR of -250 dB among GHz band SSPLLs.
This work achieved the lowest RMS jitter of 77 fs and the lowest FoMRJITR of −250 dB among them. The FoMs of GHz-band SSPLLs and mmW-band frequency synthesizers are compared on the left and right of figure. Among all mmW-band frequency synthesizers, the proposed mmW-band frequency synthesizer achieved the lowest RMS jitter and the lowest FoMRJITR.
Process 65nm CMOS 130nm CMOS 65nm CMOS 65nm CMOS 65nm CMOS Architecture Digital SSPLL Analog SSPLL Digital SSPLL Digital SSPLL Analog SSPLL. Topology OSVC-based SS-PD-based ADC-based ADC-based SS-PD-based Type Integer-N Fractional-N Fractional-N Integer-N Integer-N.
Conclusion
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