Submitted in fulfillment of the requirements for the degree of Master of Science in Electrical and Computer Engineering

The key message of the thesis is the optimization of preamplifier designs for HPGe detectors, yielding significant improvements in performance characteristics. The research contributes to the field of preamplifier design for HPGe detectors by providing valuable insights into the optimization of preamplifier designs, demonstrating significant improvements in performance characteristics. I am grateful to my family and friends for their unwavering support, love and encouragement throughout my academic journey.

Introduction

Aims and Objectives
Methodology
Problem Statement
Background Information

Charge Sensitive Amplifiers

Related Works

Summary

The design of preamplifier for HPGe detectors is mainly dependent on maintaining the essential parameters of the output signal. To simulate the performance of the preamplifier designs, the Orcad CAPTURE CIS software from Cadence has been chosen. The literature review has been conducted in the relevant area of the research topic, strictly concentrated on the research related to the preamplifier for HPGe detectors.

The scheme is also equipped with a quick reset device to perform a quick desaturation of the signal. The goal of all designs is to provide amplification and a low noise rate of the signal.

Fig. 1.1 indicates the basic concept of charge amplifier operation with an integrated process using parallel RC circuit

Preamplifier Designs Analysis

Low-Noise Charge Amplifier for the LEGEND-200 Cooperation analysis

This chapter will introduce and illustrate the analysis of various optimal CSP preamplifier designs by simulating results and overall performance comparison. The general circuit structure of the pre-amplifier and post-amplifier collimated block can be seen in Fig. The load input is applied to Q4 and Q9, configured as common-source JFETs, which provide high input resistance and relatively high gain.

𝑟 is the impedance ratio between the drain and the source, which is applied to the channel length modulation configuration and is described as in Eq. In the second stage, the signal is applied to Q3, in the configuration of the common gate, which ensures the elimination of the degree of input capacitance of the input signal. The third stage is Q1 and Q2 cascaded 2 JFETs in common source configuration, providing the current source.

The resulting amplified and shaped signal passes through source follower Q5, which has a relatively high input impedance and maintains a gain of the signal at 0. Finally, the output was passed to the post-amplifier subsystem using a push-pull driver, implemented by two JFETs Q6 and Q7 complementing each other [1]. At the same time, the other one works as non-inverting and only amplifies the signal.

However, to still maintain the functionality of the low-pass filter, the capacitance rate of C6 must be much lower than C2 [1].

Figure 2.2: Preamplifier block diagram [1]

Wide-Dynamic-Range Fast Preamplifier analysis

The high magnitude of transconductance makes it possible to maintain a low time constant of the rising edge 𝜏, which is one of the most important parameters that slow down the speed of CSP operation. The design is also equipped with 3 BJTs, which play the basic role of voltage amplification due to the lack of power supply. The feedback network of the design is represented by the parallel connection of the feedback capacitor and resistor.

The capacitor acts as a high-pass filter that removes low-frequency noise from the input signal, while the resistor provides a feedback path for stabilizing the amplifier's gain. The rise time of the final signal is 14.68 ns, while the resulting voltage amplitude is 430.27 mV.

Table 2.2: Preamplifier schematic components list

Comparison of Circuits

Wide-Dynamic-Range Fast Preamplifier
Low-Noise Charge Amplifier for the LEGEND-200 Cooperation

The research work presented in [1] introduces a preamplifier circuit for high-capacitance detectors that focuses on optimizing energy resolution and pulse shape discrimination. To achieve improved energy resolution without affecting response time, the circuit integrates a creative feedback scheme. Improved energy resolution: An inventive feedback scheme allows for better energy resolution, which is critical in many applications.

Pioneering Feedback Scheme: The characteristic feedback mechanism plays a significant role in the circuit's overall performance and energy resolution. Wide compatibility: The circuit can work with different detector types, making it an ideal choice for a variety of applications. Both circuits are designed to address the challenges associated with high-capacity detectors and pulse shape analysis.

The high-speed wide dynamic range preamplifier excels in dynamic range and response time, making it an ideal choice for applications that require a high degree of versatility, such as nuclear spectroscopy and particle identification. In contrast, the circuit presented in another research paper favors energy resolution and pulse shape discrimination through its innovative feedback scheme. Although both circuits have low noise and compatibility with a variety of detector types, the high dynamic range fast preamplifier circuit places a stronger emphasis on gain linearity and stability.

The appropriate choice between these two circuits ultimately depends on the specific requirements of an application, such as the desired dynamic range, energy resolution, and response time.

Model Description and Results

Preamplifier Schematic Study

The circuit uses the capacitance 𝐶 as part of the main feedback loop, making it a charge amplifier. The preamplifier design requires a fast gain node to maintain a low rise time of the output signal. The results of the analysis showed a clear dominance of operational amplifiers manufactured by Analog Devices.

As a next step to improve the gain coefficient, the feedback resistance of the operational amplifier was calibrated. The performance of the input FET was also tested on the output node of the FET. Specifically, the operation of Q2 and Q3 and their effect on the overall performance of the design were studied.

The aim of the experiment was to achieve better rise time and gain results. As the results of preamplifier design analysis and simulation tests, a new preamplifier circuit design with modified parameters was studied. First, the amplifier node of the circuit performance analysis scheme was simulated with a detector capacitance of 50 pF.

The operational amplifier used showed a significant slowing of the rise time by increasing the value to almost 4 ns. As a result, the return line of the op amp has been calibrated to achieve higher gain while maintaining low noise and fast rise time. The gain node of the preamp has also been modified by changing the BJTs used in the circuit.

Table 3.1: Preamplifier specification with BF862 [2]

PCB Design

Feasibility study of the chip fabrication

Opportunities and Barriers
Detailed Process of Chip Fabrication
Features of Chip Fabrication
Companies and Industries in Chip Fabrication

Manufacturing process limitations: Integrating certain features of the preamplifier circuit, such as high-voltage components or custom passive components, into standard chip manufacturing processes can be challenging [21]. Initial investment: Developing a preamplifier circuit for chip manufacturing requires a significant initial investment in design and manufacturing, potentially making it prohibitive for small-scale production or research projects [22]. Schematic design: Design and simulate the preamplifier circuit using a schematic capture tool such as Orcad Capture CIS or Cadence Virtuoso [23].

Parasitic extraction and post-layout simulation: Extract parasitic elements from the layout and perform a post-layout simulation to ensure that the chip design meets performance specifications [24]. Adaptability: Chip manufacturing allows the design to be customized to meet specific performance requirements or to optimize for specific detector types [27]. Semiconductor foundries: These companies specialize in the production of integrated circuits based on designs from their customers.

Electronic design automation (EDA) companies: These companies develop software tools used in the design, simulation, and verification of integrated circuits. Integrated Device Manufacturers (IDMs): IDMs are companies that both design and manufacture their integrated circuits. Fabless semiconductor companies: These companies focus on the design of integrated circuits and outsource the manufacturing to semiconductor foundries.

Semiconductor IP (Intellectual Property) Providers: These companies develop and license reusable circuit designs, known as IP cores, to help speed chip design and reduce development costs.

PCB Design CAD file

Supplier Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key. The bill of materials (BOM) is a crucial document for PCB and chip manufacturing as it lists all the necessary components required for the manufacturing process. This important document lists every single component needed for manufacturing, so it's critical to make sure everything is available and accounted for before production begins.

The BOM also serves as a reference for quality control, to ensure that the correct components are used during the manufacturing process. Table 4.1 in this paper provides a detailed breakdown of all the components required for PCB manufacturing, including their quantities, footprints and manufacturers.

Summary

The chapter includes the development of the PCB design for the circuit, which requires real-time implementation and verification under various conditions before proceeding with the chip design. The complexity and significant costs associated with the production of chip design require a careful approach, which ensures the elimination of errors throughout the process.

Conclusions

Pullia, "A low-noise charge amplifier with fast rise time and active discharge mechanism," in IEEE Transactions on Nuclear Science, vol. Riboldi, "A JFET-CMOS Fast Preamplifier for Segmented Germanium Detectors," in IEEE Transactions on Nuclear Science, vol. Pascovici, “Design and Optimization of Low-Noise Wide-Bandwidth Charge Preamplifiers for High Purity Germanium Detectors,” in IEEE Transactions on Nuclear Science, vol.

Pullia, "Design of an integrated low-noise, low-power charge sensitive preamplifier for γ and particle spectroscopy with solid state detectors IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2014, pp. Zocca, "Extending the dynamic range of a charge preamplifier far beyond its saturation limit: a 0.35μm CMOS preamplifier for germanium detectors." Riboldi et al., "A low-noise charge sensitive preamplifier for Ge spectroscopy operating at cryogenic temperature in the GERDA experiment work," IEEE Nuclear Science Symposium & Medical Imaging Conference, 2010, pp.

Ur, "A versatile low-noise wide-range charge-sensitive preamplifier for HPGe detectors IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC), pp. Frontini, "Design of an integrated low-noise ultra-fast charge - sensitive micro-probe for semiconductor detectors IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC), pp. Capra, “Design of a Resistorless ASIC Preamplifier for HPGe Detectors with Nonlinear Pole/Zero Cancellation and Controlled Fast-Reset Function IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC), pp.

Pagano, “Wide-dynamic-range fast preamplifier for pulse shape analysis of signals from high-capacitance detectors,” in IEEE Transactions on Nuclear Science, vol.