8-BITS X 8-BITS MODIFIED BOOTH 1’S COMPLEMENT MULTIPLIER
by
NORAFIZA SALEHAN
Report submitted in partial fulfillment of the requirements for the degree
of Bachelor of Engineering
(Electronic Enginering)
ACKNOWLEDGEMENT
I would like to take this opportunity to thank everybody who helped in any way for this project. I would like to express my gratitude and respect to my project supervisor, Madam Norina Idris for her advice, guidance, supervision, patience and understanding throughout this project.
I would like to thank my friends for all their support and friendship and I would like to wish them good luck in their future. To my family especially my parents, for their love, support and encouragement.
Last but not least, to the School of Microelectronic Engineering of Universiti Malaysia Perlis for providing the facilities that enable the success of this project.
PENDARAB 8-BIT X 8- BIT PELENGKAP 2 TERTANDA BAUGH-WOOLEY TERUBAHSUAI
ABSTRAK
Dengan kemajuan dalam teknologi, banyak penyelidik telah cuba dan mencuba mereka bentuk pendarab yang menawarkan samaada – kelajuan yang tinggi, penggunaan kuasa rendah, dan penggunaannya dalam Kamiran Berskala Sangat Besar, oleh itu membuatkan ia sesuai untuk pelbagai penggunaan seperti kelajuan tinggi, kuasa rendah Kamiran Berskala Sangat Besar yang padat. Projek ini memberi tumpuan kepada kelajuan Pendarab 8-Bit x 8-Bit Pelengkap 2 Tertanda Baugh-Wooley Terubahsuai.
Tiga cara untuk meningkatkan kelajuan pendarab – mengurangkan bilangan produk- produk separa, menambahkan kelajuan penambahan produk-produk separa dan
‘pipelining’. Kelajuan Pendarab 8-Bit x 8-Bit Pelengkap 2 Tertanda Baugh-Wooley Terubahsuai, ditingkatkan dengan mengurangkan produk-produk separa dan kemudian menjumlahkan produk-produk separa ini dengan menggunakan ‘Carry Save Adder’.
Analisis kelajuan prestasi Pendarab 8-Bit x 8-Bit Pelengkap 2 Tertanda Baugh-Wooley Terubahsuai ini dibuat menggunakan Altera Quartus II . Projek ini membuktikan bahawa Pendarab ’ mempunyai prestasi kelajuan yang tinggi dan analisa kelajuan pada EPF10K70.
ABSTRACT
With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed, low power, and compact VLSI implementation. This project focuses on speed performance of the Modified Baugh- Wooley Two’s Complement Signed Multiplier. Three methods to improve speed performance of the multiplier – reduce the number of partial products and accelerate the accumulation have been discussed in literature view. For Modified Baugh-Wooley Two’s Complement Signed Multiplier the speed is improved by reducing the partial products and then summing these partial products using Carry Save Adder. The schematic design as well as speed performance analysis of this multiplier is done using Altera’s Quartus II Software and speed obtained on EPF10K70.
TABLE OF CONTENTS
Page
ACKNOWLEDGMENT
APPROVAL AND DECLARATION SHEET i
ABSTRAK ii
ABSTRACT iii
TABLE OF CONTENTS iv
LIST OF TABLES vi
LIST OF FIGURES vii
CHAPTER 1 INTRODUCTION
1.1 Background History 1
1.2 High Speed Multiplier 2
1.3 Objective 3
CHAPTER 2 LITERATURE REVIEW
2.1 Introduction 4
2.2 High Speed Multiplier 4
2.2.1 Array Multiplier 5
2.2.2 Tree Multiplier 6
2.2.3 Booth Multiplier 7
2.3 Modified Baugh-Wooley Two’s Complement Signed Multiplier
2.3.1 Two’s Complement System 7 2.3.2 Modified Baugh-Wooley Two’s Complement Signed Multiplier 8
Page CHAPTER 3 METHODOLOGY
3.1 Introduction 12
3.2 Flow Chart of the Project 13
3.3 Subcircuits Design 14
3.3.1 AND Gate 15
3.3.2 NAND Gate 15
3.3.3 Half Adder 16
3.3.4 Carry Save Adder 17
3.3.5 D Flip-flop 19
3.4 The Design of Modified Baugh-Wooley Two’s Complement
Signed Multiplier 20
3.5 Approaches to Increase the Speed Performance of the Modified
Baugh-Wooley Two’s Complement Signed Multiplier 22 3.5.1 Reduce the Partial Products 22 3.5.2 Accelerate the Accumulation 23
3.5.3 Pipelining 25
CHAPTER 4 RESULTS AND DISCUSSION
4.1 Introduction 27
4.2 Half Adder 27
4.3 Carry Save Adder 28
4.4 Modified Baugh-Wooley Two’s Complement Signed Multiplier 29
CHAPTER 5 CONCLUSION
5.1 Summary 37
5.2 Recommendation for Future Project 38
REFERENCES 39
Figures No. Page
3.10 Modified Baugh-Wooley Two’s Complement
Signed Multiplication [9] 23
3.11 Dependence Graph for the 4-bits x 4-bits Carry Save Array
Multiplier 24
3.12 A Carry Save Vector Merging 25
3.13 Non-pipelined Version 25
3.14 Pipeline Version 26
4.1 Logic Diagram of Half Adder 27
4.2 Simulation Waveform of Half Adder. 28
4.3 Logic Diagram of Carry Save Adder. 28
4.4 Simulation Waveform of Carry Save Adder 29
4.5 8-bits x 8-bits Modified Baugh-Wooley Signed Multiplier 30
4.6 Simulation Waveform of Both Positive Numbers Multiplication 31
4.7 Simulation Waveform of Both Negative Numbers Multiplication 32
4.8 Simulation Waveform of Positive and Negative Numbers
Multiplication 33
4.9 8-bits x 8-bits Modified Baugh-Wooley Signed Multiplier with
D Flip-flop at Inputs and Outputs. 34
4.10 Speed Performance for Modified Baugh-Wooley Signed Multiplier 35
4.11 Simulation Waveform for Modified Baugh-Wooley Signed
Multiplier 35
LIST OF FIGURES
Figures No. Page
1.1 Mutiplication Example 1
2.1 4-bits x 4-bits Array Multiplier [6] 5
2.2 A Multiplier with Wallace Tree [6] 6
2.3 Two’s Complement and One’s Complement Representations 7
2.4 Unsigned Multiplication [9] 9
2.5 Two’s Complement Mutiplication [9] 9
2.6 Baugh-Wooley Two’s Complement Signed Mutiplication [9] 11
2.7 Modified Baugh-Wooley Singed Two’s Complement
Multiplication [9] 11
3.1 Flow Chart of the Project 13
3.2 Logic Diagram of Two Input AND Gate 15
3.3 Logic Diagram of Two Input NAND Gate 16
3.4 Logic Diagram of Half Adder 16
3.5 The (3,2) Counter Block Diagram 17
3.6 Logic Diagram of Full Adder 18
3.7 Block Diagram of D Flip-flop 19
3.8 Tabular Form of Bit-Level Modified Baugh-Wooley
LIST OF TABLES
Tables No. Page
3.1 Truth Table for A Two Input AND Gate 15 3.2 Truth Table for A Two Input AND Gate 16 3.3 Truth Table for Half Adder 17 3.4 Truth Table for Full Adder 19 3.5 Truth Table for D Flip-Flop 20 5.1 Performance of Modified Baugh-Wooley Two’s Complement
Signed Multiplier 38
