nano nano fabri layer meth two w imple 0.6 µ were temp effec barri drain Keyw micro trans
nano two Amo lengt
Fabrica gate ju micros Arash D Hutagalu Mohamm
1Departm Malaysia
2School of Nibong T
3Departm Putra Ma
4Departm Behbahan
5Departm
Abstrac The fabr owire transis owire patter cated with r has a thick hod impleme wet etching emented to µm/s and 8.
e elaboratel perature and ct principle, er in the ga n current to
words: Lo oscope (AF sistor (JLSN 1. Intro Departin otechnology main probl ong the seve
th of MOSF
ation and unctionles
copy nan ehzangi1, F ung2*, M. N madi5 ment of Physi a, 43400 Serd of Materials a Tebal, Penang ment of Electr
alaysia, 4340 ment of Chem n, 63617131 ment of Physi
ct
rication of stor (JLSNW rned on lig
an atomic kness of 90 ented for sa g steps, KOH
reach the s 5 volt respe ly optimize d humidity.
when essen ating region drive the de ocal anodic FM), double NWT).
oduction ng from mi y. Relevant o
lems; fabric eral types of FETs create
d characte s silicon n olithogra arhad Larki N. Hamidon3
ics, Faculty o dang, Selang
and Mineral g, Malaysia.
rical and Ele 00 Serdang, S mistry, Islami
98, Iran.
ics, Payame N
Double ga WT) was inv ghtly doped
force micro 0 nm and a
ample prepa H etching fo structures. T
ectively. Sc ed by 30%
The structu ntial positiv n. Negative evice into ac c oxidation
e gate (DG
croelectron obstacles ri cating the s f nanotransi d some issu
erization nanowire aphy
i1, Jumiah H
3, Masoud G
of Science, U gor, Malaysia l Resources E ectric Engine Selangor, Ma ic Azad Univ
Noor Univer
ate (DG) a nvestigated i d (105 cm-3 oscope (AF resistivity ( aration. The for Si remov The writing can speed w
% wt. KOH ure is a gat ve gate volta e gate volta
ccumulation n (LAO), G) and singl
nic to nano- ise up from structure an
istors, scalin ues such as
of p-type transisto
Hassan1, E.
Gharayebi4,
University Pu a.
Engineering, eering, Facu Malaysia.
versity Behba rsity, Shiraz
and Single in this resea
3) p-type si M) nanolith (ρ) of 13.5- e local anod val and HF speed and was held in 1
H + 10%
ed resistor age is appli age is unabl
n mode.
silicon-on-i e gate (SG)
-electronics this depart nd understan
ng down th short chann
double ga r by atom
B. Saion1, S Alireza Kh
utra Malaysia Universiti S lty of Engine ahan Branch, 71365-944, I
gate (SG) arch. The tra ilicon-on-in hography te -22.5 Ω cm.
dic oxidation etching for applied tip 1.0 µm/s. T vol. IPA i turned off b ed and mad le to make insulator ( ) junction-l
s is one of ing process nding the tr e size of tra nel effect (S
ate and si mic force
Sabar D.
harazmi1, Sa
a, Serdang, S Sains Malays
eering, Unive , University Iran.
Junctionle ansistors us nsulator (SO
echnique. T . The modi n (LAO) fol
oxide remo voltage we The etching in appropri based on a de a sufficie significant (SOI), atom
less silicon
the crucial s could sum ransport ph ansistors an SCE), leakag
ingle
anaz
Selangor, sia, 14300
ersity of Street,
ss silicon sed silicon OI) wafer The top Si fied RCA llowed by oval, have ere held in processes iate time,
pinch-off ently large effect on mic force
nanowire
l areas in mmarize in henomena.
d the gate ge current
46
or very low current. Several methods suggested to conquer these problems, such as high κ dielectrics [1-2], metal gate electrodes [3], and new transistor architectures based on silicon- on-insulator (SOI), such as FinFETs [4], multigate FETs [5] or gate-all-around FETs [6].
Junction less transistors (JLTs) can be a reliable alternative for the conventional scaled MOSFETs. The JLTs have a constant doping concentration through the source, channel and drain. From the first JLT [7] until recent alternatives for SOI-JLT [8-9], high doping concentration have always been recommended, in order to compensate the low number of charge carriers in the channel. But high doping always gives rise to strong unavoidable scattering effect and also increases subthreshold swing (SS) fluctuation. JLTs appeared to be the new and promising alternative for new generation of transistors [7, 10]. In the last two years, the research in JLTs focused to design and property [9, 11-12], simulation [13-14], high temperature performance [15], new fabrication method of the device with higher mobility and better performance [16-17].
The principle of AFM nanolithography, using Local anodic oxidation (LAO) on SOI, has been described for the first time by Snow and Campbell et al. [18-19]. Ionica et al. [20]
have remarkably reported the electrical characteristics of the devices made by AFM nanolithography. Also some recent works were performed to improve the method of AFM nanolithography [21-22]. However, the lack of sufficient explanation for the behaviour of these structures is still an interesting issue. It was already reported that the fabrication of the p-type side gate JLT device with simple structure, low doping concentration and no gate oxide layer [23-24]. The conventional MOSFETs functions are strongly dependent on the oxide layer and capacitance of the gate oxide layer, but for JLSNWTs, capacitance dependence does not have a strong effect [25-26]. Therefore, in our JLTs devices, lacking of the gate oxide layer could be acceptable. Moreover, it can eliminate the difficulty of the gate oxide layer stacking into the structure. In this work, the experimental method and investigation of the experimental of the side gate JLT device was improved with optimized geometry. The pinch-off effect for positive gate voltage and the effect of negative gate voltage on channel will be investigated as well. The numerical origin of double gate (DG) and single gate (SG) JLSNWT structure’s characteristic in on state at low and high drain voltages were explored according to JLT principles.
2. Methodology
The process of fabrication of double gate (DG) and single gate (SG) JLSNWT by means of AFM-LAO nanolithography on SOI substrate will be elaborately expressed. The fabrication process is divided into three separate and major steps which are shown in Fig. 1.
The important contributing parameters or factors in fabrication process can be mentioned as the cleaning and preparation procedures, AFM instrument parameters, relative humidity, KOH etching parameters, etching optimization.
2.1 Cleaning and Preparation
The first step of fabrication is the cleaning process, which was applied by modifying the standard RCA method. During optimization of the cleaning process, the ratio of chemical concentration, temperature and time are the major parameters. The standard method and other researchers suggested that the ratio of chemical 1:50 for HF:DIW.
However, in our case this ratio caused some roughness on the surface of the samples. The best ratio found for our condition was 1:100 for HF:DIW. The temperature and temperature interval are also important. Any change more than 3oC in temperature interval, exceeding
the te to in perox found ultras aceto
Fig
after it fro of th be im befor
emperature nequality or
xide/deioniz d that it di sonic clean one/methano
Fig. 1: Fl
. 2: AFM im nativ The timi each step, om long tim he sample. In
mportant in re and after
of 80oC or r even twi zed water ( id not go w ning befor ol washing
low chart of
mage of the S e oxide and ing of imme
the sample me air expos n addition, each step o cleaning pr
lowering be sting the s H2SO4/H2O well with th re applying before the R
methodology
SOI substrate other contam ersing or ev
was immed sure which
it was also of the clean
rocess.
elow 77oC d sample surf O2/H2O) at 1 he SOI sur g the RCA
RCA cleani
y and steps o nanolithogra
e (a) before, a mination rem ven rinsing diately put
will caused found that ning. Fig. 2
during the c face. By ap 110-130oC
face due to A method ing also did
of fabrication aphy.
and b) after o moval is recog
is also very into the bea d the native
the type an shows the A
cleaning pro pplying sul in Piranha c o high temp was very not produc
n the device b
optimized RC gnizable after y important
aker contain oxide appe nd brand nam
AFM image
ocess would ulfuric acid/
clean metho perature. Th useful. U ce good resu
by AFM-LA
CA cleaning r cleaning.
factor. For ning DIW t earing on th me of SOI w es of the SO
47 d give rise /hydrogen od, it was he use of Using the
ults.
AO
g process,
examples to prevent he surface wafer can OI sample
48 2.
T process S surface w electron from hum when the between Not only direction W process.
speed of High volt surface. T writing s speed did speeds of of 0.6 µm
Fig. 3: E
A to water thickness strength a voltage. I constant
.2 Contrib The oxide gr Si-H bonds was de-pas negativity o midity to for e OH- drifted
the first sili y the electr n to cause th Writing spee
Fig. 3 show f 0.6 µm/s a
tage (Fig. 3 The best res speeds can d not provi f 1.0 and 1.5 m/s and the v
Effective par different a Another para molecules s of oxide in
at high RH%
In Fig. 4, th applied vol
bution of A rowth mech are formed sivated, the of the OH-. rm monolay d through th icon oxide rical fields he OH- diffu ed and AFM ws the effe and for diff 3(a), (b)) pro
sult was der make wide ide any oxid 5 μm/s the o voltage of 8
rameters dur applied volta ameter play in the amb ncreased sim
%. The oxid he relation b tage of 8.5
pplying Vo hanism can b
on the surf e first laye . Then, the yer of silico
he oxide film layer and th
enhanced t usion throug M tip voltag
ct of applie ferent writin ovides thick rived from t er oxidation dation effec oxidation tr 8.5 V are th
ing LAO pro age on AFM
s an import bient air fo multaneousl de thickness between ox
V is shown
oltage on th be describe face and nat er of Si-Si Si-Si bond on oxide, SiO
m. It happe he substrate the OH- fo gh the oxide ge are two ed voltage ng speeds w ker oxidatio
the applied n effect on ct on the su racks were n he optimized
ocess on diff tip and c) ef tant role in L or oxidation
ly. The oxid s extremely xide thickne n.
he AFM Tip ed as the fol
tive oxide c bonds beca ds reacted t
O2. The oxi ened when th
e when appl ormation, bu
e film.
parameters on the AFM with the sam on and more
voltage of 8 n the substr
ubstrate in not recogniz d parameter
ferent arbitrar ffect of differ LAO is the n process.
dation rate y depends on ess and RH%
p and Expo llowing [27
ould be rem ame polariz to the polar ide film thic he electric f lying a volta ut also pro
to optimiz M tip at a me applied e uniformity
8 V. On the rate, wherea 8V (Fig. 3(
zable. In ou s.
ry samples a rent writing s
relative hum When RH%
is very sens n the humid
% at room t
osure Time 7]. After cle moved. Whe
zed due to r H2O mole ckness incre fields are cr tage on AFM ovide the co ze the fabric constant w d voltage of y on the sub e other hand
as faster w (c)). For w ur case, the
a) and b) effe speed.
midity (RH)
% increased sitive to the dity and AF temperature
e aning en the high ecules eased, reated M tip.
orrect cation writing f 8 V.
bstrate d, low writing writing speed
ect of
), due d, the e field
M tip e with
Fig
Norm humi in the for th oxide supp in ox show shado repor
Fi
g. 4: Relation
Humidity mally to get
idity must b e range of 2 he Cr/Pt co e thickness
ort the prev xide growth ws the AFM ow around rted in seve
ig. 5: AFM to
n between ox
y and tem t a good pa be ≤ 4%. Fr 22 – 26oC f oated tip. In
will be re vious studie h on silicon M topograph
the pad can eral works [3
opography im
xide thicknes
mperature ar attern, the r rom the obs for the temp n fact, after educed, inst es on AFM n
surface wh hy for the p
n be seen, w 30] and our
mages of the
ss and RH % voltage (8.5 re affecting range of tem
ervation du perature and r RH% inc tead, the sh
nano-oxida hen the othe pads prepare which deform
r observation
e pads with th
, at room tem 5 V).
g the devic mperature m uring pattern
d between 6 creases beyo
hadow effe ation about t ers paramet ed by LAO
med the sha n has confir
he shadow ef
mperature wi
ce structure must be ≤ 4 ning, the be
5-68% for t ond 70% th ct was obs the influenc ters are con technique.
ape. This ph rmed this.
ffect due to L
ith constant a
e during p 4oC and the est results w the relative he rate of i served. The ces of room nstant [27-2 The presen henomenon
LAO in high
49 applying
patterning.
e range of were found humidity increasing ese results m humidity
29]. Fig. 5 nce of the n has been
RH %.
50 2.
K having c etching, a area, KO 33], it ca increased precipitat cleaning making t roughnes literature the KOH temperatu nanostruc KOH con immersin Fig. 6(b) concentra complete that for nanowire the gap a IPA [33, a pyrami the differ 8(b)) on time. Som of KOH.
compare
Fig. 6: SE wt. KO
.3 Effect o KOH wet et
contaminatio accordingly OH was used
an be clearly d. At low K
tes can be s process. IP the etching ss increased es for optimi H etchant. A
ure are als cture forma ncentration ng time of 2
), (c). In F ation, the s e structure b
the over e/channel ha area. In fact 35-36]. In d shaped et rent concen the structur me parts of . It can be to higher im
EM images o OH + 10% vo
seconds,
of KOH Etc tching is a v
on, ill-etch y, the accura
d as etchant y seen that t KOH concen seen. Isopro PA reduced process m d drastically ization, the Apart from so playing ation. In Fi
are shown 20s (Fig. 6(a ig 6(a), (b) harpness w before etchi etched sa as disappear t, it would h anisotropic tch pit and t
tartion of K re for 40%
f the structu said that fo mmersing ti
of the nanow ol. IPA for 2 and c) etche
ching Proce very signifi ed or over acy and prec
t. Referring the surface ntration, the opanol (IPA d the etch r more control y when add
best percen the concen important g. 6, SEM n. With the
a)), structur ) also can will be decre
ing and afte ample (Fig red and the have anisot
etching for the wall wil KOH for two
wt. KOH re are clear for higher c ime or temp
wire and the l 20 seconds, b ed with 40%
ess on Devi ficant part in
r etching st caution are g to the prev
roughness i e surface wa A) was used rate, hence llable [32].
ded the IPA ntage of IPA
ntration of role in ob images un e solution o re shows pro
be seen fo eased. In F er etching (o g. 7(b)) th gate contac tropic etchin r (100) Si, th ll be flat and
o complete + 10% IPA rly gone due concentratio perature.
lateral gate g b) etched wit wt. KOH +
ice Fabrica n the fabric tructure wa important.
vious report improved a as rough and
in this work improving Moreover A [31, 34].
A added to t f the etchan btaining the nder the eff of 30% wt.
oper sharpn or longer im
ig. 7, AFM over etched he gap be ct expanded ng to the str he rectangu d angled. Fi structures a A at 65oC, a e to re-etch on, over etc
gap at room t h 30% wt. K 10% vol. IPA
ation cation of JL as hardly a
To remove ts in KOH w s the conce d the forma k as initiato the surface , the unifor Base on th the solution nt, the imm e most opti fect of etch
KOH+ 10 ess compar mmersing ti M topograph d) are shown
etween the d toward the ructure etch ular hole wil ig. 8 shows and over et after 30 sec
ing with hig ching would
temperature, KOH + 10% v A for 20 seco
LSNWT. In avoidable in
the undesir wet etching entration of ation of inso
or to improv e roughnes rmity of su his work an n was 10% v mersing time imum resu hing for diff
% vol. IPA re to the oth
ime at the hy images o n. It can be e gate and e channel an hed with KO
ll be ended SEM imag tching effec conds imme
gh concentr d be more
a) etched w vol. IPA for onds.
n fact, n wet red Si g [31-
KOH oluble ve the s and urface nd the vol. in e and lt for fferent A and hers in
same of the e seen d the nd fill
OH + up in es for t (Fig.
ersing ration sever
with 30%
28
Fig etch
Fig. 8 wt. K
and a clean etchi is to
hydro etchi was e remo nativ
expo able must
g. 7: AFM to hed) with the
8: SEM imag KOH + 10%
2.4 Opt In this st adopted [23 n room and ing at 63oC, ensure the u
2.5 Effe The oxi ofluoric aci ing by KOH
etched with ove the SiO ve oxide and 2.6 Oth In fabric osure time o to make sig t be specif
opography im e solution of
ges for the co IPA at 63oC
KOH + 1
timum Con tudy, previo 3, 33, 37-41
other param , 20 second uniformity o ect of Oxid ide reoval id (HF) in a H admixture h diluted HF O2 mask. D
d the mask w her Parame cation proce or cleaning gnificant eff fied for co
mages of the f 30% wt. KO
omplete struc , after 23 sec 10% IPA at 6
ndition for ous works fo
1]. The bes meters is the
s for immer of the etchin e Removal
is the las aqueous sol e with IPA F at room te uring HF e were remov eters Issues ess, in additi and prepara fect in detai ontact mod
structure a) b OH + 10% IP
cture after et conds immer 63oC, after 23
KOH Etch for optimum st condition
e solution o rsing time a ng process.
l on Device st step in lution with solution, th emperature f etching oxid ved.
s
ion of majo ation proce ils. The typ de (tapping
before, and b PA at 68oC, a
tching proces rsing time, b) 3 seconds im
hing m condition
according of 30% wt. K
and stirred a
Fabricatio our fabric well-known he Si layer s for 12-14 se de removal
or factors lik ss, there are e of the AF g mode an
b) after the et after 30 seco
ss a) etched b ) etched by th mmersing tim
for KOH et to the fabr KOH with 1
at 600 rpm.
on
ation meth n ability to should be re econds and l, the oxide
ke RH% or a e some min FM tip is ver nd non-con
tching proce onds immersi
by the soluti he solution o me.
tching are c rication env 10% vol. IP Stirring th
hod. The e dissolve Si removed. Th stirred at 6 e layer incl
applying vo nor factors w
ry importan ntact mode
51 ess (over
ing time.
on of 30%
of 40% wt.
onsidered vironment, PA for wet e solution
etchant is iO2. After he sample 00 rpm to uding the
oltage and which are nt. The tip tips are
52 nonfunct coated, C condition coating l probe als tip got is A pattern st been prov proper hu
Fig. 9:
T fabricatio native ox [24]. The uncovere property.
and HF e images fo recognize
ional). For Cr/Pt coated n of the exp
ayer also en so showed th more reliab Another issu
tructure can vided. Fig.
umidity in a
AFM image The unwant
on should b xide could b e one of the ed Si layer r
. For examp etching of (0 for the over
ed that som
Fig. 10:
this case t d conductiv periment, th
nhances the he acceptab ble result.
ue is the ord nnot be mad 9 shows th ambient air
of successiv pr ted native be considere be probably
e important removal. It ple, the imm
001) Si waf etching eff me parts of th
: SEM image
three types ve probe an e best resul e laser refle ble result [2 der of oxida de in one tim hat the secon
to make the
ve LAO for t oper humidit
oxide laye ed, even th y the import t issue face could be ve mersing tim
fer is differe fect of high he structure
es for over et
of contact nd Al reflex lt extracted ectivity of th
3, 33, 42], b ation. By ex me unless, p nd pad (righ e perfect LA
two pads the ty in ambien er on the t hough the s tant reason ed during th ery tricky an me or temper
ent with ano h concentrat
were remo
tched sample
mode tips x coating. R
by Cr/Pt co he cantileve but with Cr xperiment, proper hum ht side) is i AO.
right pad is nt for LAO.
top of the ample was for Hystere he fabricatio
nd sometim rature for K other orient tion of KOH
ved.
e after KOH
were test, Regarding oated condu
er. In fact g /Pt coated c it was learn midity in am
ll-shaped d
ill-shaped du sample a keep at dry esis effect re
on was in K mes it depen
KOH etching tation [43].
H+IPA are s
and HF etchi
which wer to the parti uctive probe gold (Au) c conductive p nt that the w mbient air al
due to the la
ue to the lack while afte ryer cabinet eported for KOH etchin nds in the su ng for Si rem
In Fig. 10, shown. It c
hing.
re Au icular e. The coated probe whole ready ack of
k of er the
t. The work ng for urface moval SEM an be
of D drain Acco have and 4 with side, for S
semi diffe each resol vacu to 10 +3 V chan The f show volta latera posit a pos the c pinch
3. Resu Fig. 11 s G and SG n are unifor ordingly, th 100 nm fo 4 μm for the
the channe displayed b SG structure
F For the conductor rent configu
of which lution of 1 uumed envir
0 fA of curre For the s V while kee nnel is p-typ figure show ws that the d age, the cur al gate appl tive gate vo sitive gate v channel start
h off state.
ults and Dis shows the A
JLSNWT.
rmly doped he source, d or the chann e distance b l intentiona better perfo e [23-24, 33
Fig. 11: AFM e character parametric urations. Th can supply pA. If pro ronment (th
ent.
side(s) gate eping the d pe. ID-VG gr ws the pinch device is in rrent will b lying on the oltage regard voltage is a ts to deplete
scussion AFM and SE
In Fig.11(a and made drain and ch nel width, th between the ally located ormance and
].
M and SEM im rization of
analyzer w his analyzer
upto 50 V oper cares a he SPA equi ed measurem drain to sou
raphs are sh h-off effect on state for be dropped
e channel. T ding to the p applied to th e at a suffic
EM images a), the whol of p-type S hannel wou he gate gap source and closer to th d less leakag
mages of DG f the devi were used t r has four m V with max
are taken, ipped with ment, first t urce voltage hown for SG
due to posi r zero gate v d. This indi
The field ef p-type chan he lateral g ient positiv
of profile a le structure SOI with 9 uld have the
of 100 nm d drain. The
e gate and n ge current c
G a),b) and S ice Agilen to monitor medium pow ximum curre such as the the vacuum the side gat e (VDS) con GJLSNWT
tive lateral voltage, and
cates the p ffect also ca nnel. When gate, the cur e gate volta
analysis and of the sou 0 nm thick e same thic
, 200 nm fo sample sho not in middl compared to
G c),d) JLSN nt HP4156C
current-vol wer source m
ent of 100 e cable are m facility), i
te (VG) was nstant and n
for VDS= -1 gate applyi d by increas pinch-off ef an be observ
the device rrent value age and the
d topograph urce, channe kness of the ckness. Bot or the chann own in Fig
le of the sou o our previo
NWTs.
C SPA d ltage relati monitor unit
mA and th e kept in a it can meas s swept from negative be 1, -0.05 in F
ing on the c sing the pos ffect due to rved under t
is in the on will be dro device reac
53 hic picture el and the e Si layer.
th devices nel length 11(c), (d), urce/drain ous works
device or onship in ts (SMU), he current
dark and sure down m -3 V to ecause the Fig. 12(a).
channel. It sitive gate o positive
the lateral n state and opped and ches to the
54 In MOSFET channel channel.
major car T mV/deca respectiv the gate r compare structure shows th of gate v threshold state with
L channel, (5x1019 c with high field-effe decrease of the de nanolitho cases, the
Fig.
n JLTs, the Ts where it
is depleted For p-type rriers in the The On/Off ade respecti vely (Fig. 12
regarding to to SG struc respectivel hat the drain voltage, unli d voltage (+
h zero gate v Low current
which is lo cm-3) JLTs.
h scattering ect mobility the scatteri evices have ography wit
e devices w
12: Transfer
e gate volta t is necessi d by the ga channel, in e channel to ratio and s ively (not s 2(b)). High o the chann cture. The p ly. As it is s n current (ID
ike the conv + 1.2 V for
voltage.
t is due to ower than re The MOSF effect or th y and drive ing effect an e the same th nearly sim were used as
r (a) and outp
age controls ity of rever ate electros ncreasing ne
accumulate ubthreshold shown) and
SS for the nel, which a pinch off eff shown in Fi
D) does not ventional p
SG and +0 the low d eported curr FETs or JLT hreshold vol e current. I nd threshold
trend com milar structu
the pinch o
put (b) chara
s the chann rse bias fo static potent
egative vol e, producing d swing (SS d for SGJLS e SG structu as expected ffect occurre ig. 12(a) for t significan -type chann .8V for DG doping con rent value o Ts with high
ltage variat It also can d-voltage va mpared to th ture [18, 46 off device.
acteristics gra
nel resistivit r off state tial, produc tage applied g low resist S) for DGJL
SNWT wer ure can be d for DG str
ed in +1.5 V r SG structu ntly increase nel MOSFE G), indicates ncentration of the high d
h doping co tion. Low c n be helpfu
ariations [4 he reported -47]. Howe
aph for the S
ty. Unlike t condition, cing high r d on the ga ivity [44].
LSNWT we re 105 and explained b ructure, the V and +2.5 V
ure, the outp e with the n ETs. Also, h s that the tra
profile (10 doping conc oncentration channel dop l to have l 5]. Electrica d cases fabr ever, in none
SGJLSNWT
the convent but in JLT resistivity i ate will forc
ere 106 and 167 mV/d by asymmet e SS is decr
V in DG an put characte negative inc high and po ransistor is i 015 cm-3) fo centration p n mostly suf ping can imp
low off cu al character ricated by ne of the rep
at T= 300K.
tional T, the
n the ce the d 100 ecade try of reased nd SG eristic crease ositive in On or the profile
ffered prove urrent, ristics AFM ported
55 4. Conclusion
Simple structures as the side gate Junctionless Si transistor fabricated on low-doped SOI by improved AFM nanolithography. Sample preparation and cleaning process were modified RCA method. The AFM-LAO parameters were optimized to achieve the devices.
Two wet etching process implemented to extract the structure after LAO process. First, the KOH etching to remove the uncovered Silicon and then, the HF etching for Silicon oxide removal were used. The output and transfer characteristic of the device investigated showing the device is in on state for zero gate voltage. The pinch off effect observed for positive gate voltage
Acknowledgements
The authors gratefully acknowledge that this work was financially supported by the Science Fund from the Ministry of Science, Technology and Innovation (MOSTI), Malaysia, under project no. 03-01-05-SF0384, the USM Short Term Grant under project no.
304/PBAHAN/6039035, and UPM FRGS no. 5524051.
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