Received: 27 December 2022, Accepted: 27 January 2023, Published: 28 June 2023, Publisher: UTP Press, Creative Commons: CC BY 4.0
NUMERICAL ANALYSIS STUDY OF THE EFFECTS OF BACKSCATTERING COEFFICIENT ON ELECTRICAL PERFORMANCE OF DOUBLE-GATE NANO-MOSFET
Ooi Chek Yee
Faculty of Information and Communication Technology, Universiti Tunku Abdul Rahman, Malaysia Email: [email protected]
ABSTRACT
This paper has investigated and compared the simulated and computed electrical characteristics of 10 nm double- gate (DG) nano-MOSFET with and without carrier backscattering. The electrical parameters thus studied include Ballistic Enhancement Factor (BEF), on-state ballistic drain current Id, 2D electron density Qi and electron velocity v.
BEF values with and without backscattering coefficients are 2.065 and 2.149, respectively, because injection velocity reduced when considering backscattering. Average electron velocity near the beginning of the device channel has been found to reduce from 4.131x105 ms-1 to 1.186x105 ms-1 with the inclusion of the backscattering phenomenon. The 2D electron density with and without backscattering coefficients are 3.927x1016 m-2 and 3.850x1016 m-2, respectively. The increment is because backscattered electrons and injected electrons superimposed and interfered with each other in the channel due to the wave nature of electrons occurrence in nanometer transistors. There are two current equations studied in this paper. The first is on flux theory, and the other is on the product of electron concentration and velocity.
The first method showed a current reduction from 2.548x103 μA/μm to 2.497x103 μA/μm. The second way also showed an approximate reduction from 2.548x103μA/μm to 2.497x103 μA/μm after minor modification in modeling. Both ways indicate that electrons are backscattered to the source by the potential barrier at the beginning of the channel, thereby reducing the number of electrons reaching the drain. In conclusion, backscattering is a physical phenomenon which can’t be ignored in describing electron transport in DG nano-MOSFETs.
Keywords: Simulation, theoretical calculation, transport model, nanometer, ballistic, quantum effects
INTRODUCTION
In classical bulk MOSFETs, the carriers transport model involved is a drift-diffusion equation, whereas, in nanoscale nano-MOSFETs, the carriers transport model is mainly ballistic quantum mechanical in nature [1]-[4]. Device scientists can use Technology Computer-Aided Design (TCAD) software to study and examine the transport models of both cases [5]-[6]. The main obstacle in using TCAD is the development of relevant carrier transport models software codes which are normally complex and sophisticated, especially when dealing with nanodevice quantum models. The
quantum numerical models must take into account quantum confinement in the device channel and non-equilibrium transport physics, which comprise all related scattering mechanisms [7]-[9]. Currently, there are two main physical models used in simulating nanotransistors. The first one is applying Multi Subband Monte Carlo Method for solving Boltzmann Transport Equation, but this is not the focus of this paper. The second approach is applying Non-Equilibrium Green’s Function (NEGF) formalism to solve the Schrodinger equation, which rigorously captures the wave property
of carriers, but scattering mechanisms are difficult to incorporate into this second method, especially when devices are downscaled to nanometer regimes [10]-[12].
Backscattering in quantum mechanical limits is one crucial parameter concerning the scattering events [13]-[18]. Backscattering must be included in numerical transport models for nanotransistors in order to accurately evaluate the electrical performance of the nanodevices under investigation before the nanotransistors can be commercialized to design logic circuits and electronic systems [19]-[24]. This is the reason why this study is being carried out.
DEVICE DESIGN
The symmetric 10 nm DG nano-MOSFET device structure used in this simulation study is shown in Figure 1.
Figure 1 Device structure diagram
The device simulation software used is free online nanoMOS which applies NEGF formalism to solve the Schrodinger equation. The semiconductor material used is Silicon (Si). Si is chosen because it is the most abundant material on the earth and thus eliminating any doubt about availability. Moreover, the fabrication technology of Si is mature nowadays. The device structural simulation parameters settings are listed in Table 1. The device parameters in Table 1 are chosen such that the electrons in the channel have quantum mechanical properties instead of possessing particle nature properties as in classical bulk MOSFETs. Wafer orientation is (001) with translational direction [100].
This Si (001) wafer orientation is chosen such that the device coordinate axes will be in the same directions as the constant-energy ellipsoids of the conduction band. This situation will facilitate quantum mechanical treatment and simplify the computation of electron transport in n-MOSFETs. These criteria are not satisfied in other wafer orientations, such as (111).
Table 1 Device simulation parameters settings Simulation Parameters Setting of
Double-Gate nano-MOSFET Drain-to-Source
Voltage Bias (VDS) 0.60 V Gate-to-Source
Voltage Bias (VGS) 0.60 V Threshold Voltage (VT) 0.20 V
Ambient Temperature 300 K
Source/Drain Doping
Concentration (ND) 1x1020 cm-3 Body Doping
Concentration 0 cm-3
Silicon Channel
Thickness (TSi) 1.5 nm
Source/Drain Overlap 0 nm
Source Length/Drain
Length (LSD) 7.5 nm
Channel Length (L) 10 nm
Top/Bottom Oxide
Insulator Thickness (TOX) 1.5 nm Top/Bottom Insulator
Relative Dielectric
Constant 3.9
Longitudinal Relative
Electron Mass Ratio (ml) 0.98 Transverse Relative
Electron Mass Ratio (mt) 0.19 Channel Body Relative
Dielectric Constant 11.7
Top/Bottom Gate Contact
Work Function 4.188 eV
Silicon Conduction Band
Valleys unprimed
Number of
Subbands 1
REVIEW OF THE TRANSPORT THEORY OF NANO-MOSFET
Transport Model without Backscattering This model is proposed by Natori [25] with two assumptions. Firstly, drain and source are considered
ideal reservoirs of electrons in equilibrium conditions.
Secondly, the gate controls the potential barrier perfectly, so Short Channel Effects (SCEs) can be neglected. According to this model, the semiclassical flux of electrons emitted from the source, Fs+ in equilibrium in the Si channel is computed easily as,
(1) where, mcL=mt , mcT=(ml1/2+mt1/2 )2 , i is the subband index EiL (resp. EiT ) unprimed (resp.primed)subband energies
On the other hand, the semiclassical flux of electrons emitted by drain, Fd- is
(2) where, EFd = EFs-qVDS and F1/2 is the Fermi-Dirac Integral of order ½.
(3) The above model is formulated in the quantum limit regime and can be generalized in the more general case of a multi-subband inversion layer for various materials with arbitrary wafer orientation.
In a full ballistic regime with charge distribution in k-space, when the positive k states of the conduction band are occupied by electrons injected by source reservoirs, the electron density, Ns+ flowing from source to drain is given by:
(4) where mdL = 2mt , mdT = (mlmt)1/2 and F0 is the Fermi- Dirac Integral of order zero. Whereas the negative k states of the conduction band are populated by electrons emitted by the drain and the electron density, Nd- flowing from drain to source is expressed as,
(5) For a properly designed nano-MOSFET without SCEs, the total charge at the virtual source is constant when
a voltage bias VDS is applied between the source and drain. The total charge density, Qi is given by:
Qi=qNs+(EFs)+qNd- (EFs,VDS )
In non-equilibrium conditions, there is a difference of qVDS between the Fermi level between the source and drain. At last, the net current flow from source to drain is simply expressed by:
IdBAL=q(Fs+-Fd-)
The injection velocity, Vinj is defined as the ratio between the flux of electrons injected by the source into the channel divided by the corresponding electron density, stated as:
Vinj= Fs+ N–––s+
In a high drain bias condition, that is high field situation, where nano-MOSFET is at on-state, the drain is unable to emit electrons capable of reaching the source, and the current equation is simply given by:
IdBAL~QiVinj
The product of electron density and average electron velocity actually forms this current equation.
When comparing electron transport in nano-MOSFET with those models in bulk MOSFET, one parameter of great interest to device engineers is BEF which is given by:
BEFBAL= Vinj –––Vsat
where Vsat is the saturation velocity. In other words, BEF is simply the ratio between ballistic current and drift-diffusion current.
A complete understanding of the above theories requires extensive research and sophisticated tools. All the above equations are expressed without considering backscattering [26]-[27].
Transport Model with Backscattering
Lundstrom has modified the transport model without backscattering in the previous subsection with the (7)
(8)
(9)
(10) (6)
flux theory concept to account for backscattering. The important parameter of this method is the introduction of the backscattering coefficient, r. This parameter is defined as the ratio between the flux of electrons reinjected to the source by scattering and the flux of electrons emitted by the source. The schematic diagram of this phenomenon is shown in Figure 2 as adopted from the reference [28].
Figure 2 Diagram showing the backscattering mechanism Basically, the value of backscattering is between 0 and 1.
It depends on the potential barrier within the channel, gate bias, drain bias and scattering mechanisms. In other words, the backscattering ratio is given by the following equation [29]:
r = l (l+λ)–––
where the backscattering mean free path of carriers is λ , critical length of scattering is l. The equations in the previous subsection can be improved by using this backscattering coefficient. So, Equation 6 becomes Equation 12, Equation 7 becomes Equation 13, Equation 9 becomes Equation 14 and finally, Equation 10 becomes Equation 15.
Qi= qNs+(EFs)(1+r(VDS ))+qNd-(EFs,VDS )(1-r(VDS )) Id = q[Fs+-rFs+-(1– r) Fd-]
Idsat = (1– rsat)
––––––
(1+rsat ) QiVinj
BEFQBAL = 1– rsat
–––––
1+rsat Vinj
V––sat
Backscattering determines the upper limit of average electron velocity at the beginning of the channel,
‹
v(0)›
. Under high drain bias, this average electron velocity can be related to backscattering according to the following equation:‹
v(0)›
≈ ––––(1– r)(1+r) vTwhere vT is thermal velocity given by:
vT=
√
––––2kTπmtwith mt is the effective transverse mass.
Due to the high electric field caused by high drain bias and strong velocity overshoot, electron transport at the drain end of the channel is determined by how quickly electrons are transported across a short low- field region near the source terminal of the channel.
This crucial region is called the “kT-layer”, as shown in Figure 2 because it is approximately the distance where the channel potential is reduced by kB T/q. The on-state drain current is controlled by scattering within this kT- layer. The scattering at the drain end of the channel can be ignored since it has just an indirect effect. For a well-designed nano-MOSFET, such as the structure studied in this paper, the kT-layer has a length of about one mean free path. This implies that quasi-ballistic electron transport occurs across this kT-layer.
Backscattering has to be included in the electron transport models because, in practical semiconductor nanodevices, such as DG nano-MOSFET in this study, scatterings always exist in the channel, so incorporating backscattering can accurately explain electrical performance in the real situation by equations.
RESULTS AND DISCUSSION
From Equation 11, the backscattering coefficient r is (17)
QBAL QBAL
*
*
Figure 3 Subband energy profile along the channel direction
(11)
(16)
(12) (13) (14)
(15)
0.02, where the detailed calculation can be found in reference [30]. Figures 3 and 4 show the simulation output plot of the subband energy profile and drain current versus drain voltage graph, respectively.
The conduction subband simulated is an unprimed subband with one valley. Since the energy level splitting is much larger than the thermal voltage in ultrathin nano-MOSFET, electrons can only populate the bottom subband without jumping to higher levels.
It is enough to simulate and study only one unprimed subband, as in this project. From Figure 3, Equations 1 and 3 are calculated to be 1.590 x1022 cm-1s-1 and 8.239 x 1012 cm-1s-1, respectively. Using Equations 7 and 13, the drain current without and with backscattering are evaluated to be equal to 2.548 x 103μA/μm and 2.497x103 μA/μm, respectively. At high drain bias conditions, using Equations 9 and 14 for the situation without and with backscattering, the drain current is calculated to be 2.548 x 103 μA/μm and 2.497 x 103 μA/μm,
Figure 4 Drain current against drain voltage curve
Figure 5 2D Electron density and average electron velocity along the channel
respectively. These two current models exhibited a reduction of drain current when the backscattering coefficient was introduced to the current models because electrons are backscattering by potential
barriers. Equations 9 and 14 use the current model of the product between electron concentration and electron velocity, as shown in Figure 5 [31].
Refer to Figure 5 for the 2D electron density curve.
Using Equations 4 and 5, from Figure 3, Ns+ and Nd- are computed to be 3.850 x 1016 m-2 and 5.872 x 107 m-2, respectively. Summing these two values produces the 2D electron density of 3.850 x 1016 m-2, which corresponds to a charge density of 6.167 x 10-3 cm-2 at the centre of the nano-MOSFET. From Figure 5, the simulated value of electron density is 3.4 x 1016 m-2. As stated in Equation 12, when backscattering is included, the 2D electron density is 3.927 x 1016 m-2, corresponding to a charge density of 6.290 x 10-3 cm-2. The slight increment, as observed, is considered due to interference between backscattered electrons and injected electrons with each other in the channel region. The electron density in the channel is low compared to those in the source and drain because electrons injected from the source are treated quantum mechanically and can be reflected back into the source, therefore, electron density gradually decreases toward the drain in the channel.
Electrons are also injected from the drain but can be ignored at high drain bias. Figure 6 shows the plot of 2D electron density along the channel with the subband energy profile at the secondary axis.
Figure 6 2D electron density and subband energy profile along the channel
After computing Fs+ and Ns+, the injection velocity Vinj which is obtained from Equation 8, is equal to 4.131 x 105 ms-1. Figure 7 shows the average electron velocity along the channel plotted with the subband energy profile at the secondary vertical axis.
Figure 7 Average electron velocity and subband energy profile along the channel
From the figure, the electron saturation velocity at the peak barrier is 1.922 x 105 ms-1; hence, from Equation 10, BEF is 2.149 without a backscattering coefficient, while from Equation 15, BEF with a backscattering coefficient is 2.065. Since BEF is a measure of current enhancement and so, as expected, the drain current with a backscattering coefficient will be lower as a result of lower BEF.
In Figure 7, the low energy band between 5 nm and 12.5 nm is at the region of the drain reservoir where electrons are in thermal equilibrium with an average velocity of around 1x 107 cms-1, as can be observed from Figure 7. The source terminal is biased at 0.00 V, and the drain terminal is biased at 0.60 V. Therefore, the quasi-Fermi level at the source is expected to equal 0 eV, which is around -0.1 eV as taken from the graph. Since only an electron is considered in this simulation (no hole is involved), the Fermi level at the drain is around -0.7 eV. As the electrons injected by the source, which are not reflected by potential barrier, travel to the drain due to a high electric field caused by drain bias, electrons achieved high average velocity before they enter the drain reservoir.
The thermal velocity, as calculated with Equation 17, is 1.234 x 105 ms-1. Backscattering will affect the electron velocity at “kT-layer”, which is located near the source at the beginning of the channel. From Equation 16, this velocity v(0) is roughly 1.186 x 105 ms-1, which is lower than thermal velocity. Since electron transport across the kT-layer determines the current flow, there is a decline in drain current when considering v(0) with a backscattering coefficient [32].
CONCLUSION
Electron transport models in ultrathin and ultrashort nano-MOSFETs are quantum mechanically in nature.
These models must include scattering mechanisms, such as electron-phonons and electron-impurities scattering, to accurately describe the carrier transport through the channel. In this paper, due backscattering reflection from the subband energy potential barrier has been shown to potentially influence the performance accuracy of nano-MOSFET electrical characteristics such as drain current, electron density and average electron velocity. There is a discrepancy in performance between the transport model with and without backscattering.
Therefore, all nano-MOSFET devices must be evaluated electrically with correct transport models before these nanotransistors can be commercialised to design logic circuits and electronic systems.
REFERENCES
[1] S. Mittal and A. Nandi, “Analysis of MC model & DD model on DG-MOSFET for different gate length with different gate oxide”, in Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018), 2018, pp. 817-820.
[2] S. Gulati, J.D. Pandya, and S. Save, “Performance evaluation of 30 nm double gate MOSFET using VTCAD tool”, International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering, pp. 1-8, 2018.
[3] Q. Chen, B. Agrawal and J. D. Meindl, “A comprehensive analytical subthreshold swing (S) model for double- gate MOSFETs”, IEEE Transactions on Electron Devices, vol. 49, no. 6, pp. 1086-1090, 2022.
[4] K. Yilmaz, A. Farokhnejad, F. Criado, B. Iniguez, F.
Lime, and A. Kloes, “Direct source-to-drain tunneling current in ultra-short channel DG MOSFETs by wavelet transform”, in 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020, pp. 1-4.
[5] A. Kumar Suhag and R. Sharma, “Design and simulation of nanoscale double gate MOSFET using high K material and ballistic transport method”, in Materials Today: Proceedings, 2017, vol. 4, no. 9, pp. 10412-10416.
[6] H.K. Jung and S. Dimitrijev, “Analysis of subthreshold carrier transport for ultimate DGMOSFET”, IEEE Transactions on Electron Devices, vol. 53, no. 4, 2006.
[7] Pr. Saha, P. Banerjee, D.K. Dash, and S.K. Sarkar,
“Modeling short channel behaviour of proposed work function engineered high-k gate stack DG MOSFET with vertical Gaussian doping”, in 2018 IEEE Electron Device Kolkata Conference (EDKCON), 2018, pp. 32-36.
[8] K. Yilmaz, G. darbandy, B. Iniguez, F. Lime, and A. Kloes,
“Equivalent length concept for compact modeling of short-channel GAA and DG MOSFETs”, in 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI- ULIS), April. 2019.
[9] Md. R. Hasan, “Influence of device performance of sub-10 nm GaN-based DG-MOSFET over conventional Si-based SG-MOSFETs”, in Proceedings of the 2017 4th International Conference on Advances in Electrical Engineering, 2017, pp. 697-702.
[10] F. Yu, G. Huang, W. Lin, and C. Xu, “An analytical drain current model for symmetric double-gate MOSFETs”, AIP Advances 8, 045125,2018, doi: 10.1063/1.5024574 [11] R. Vaddi, R.P. Agarwal, and S. Dasgupta, “Compact modelling
of a generic double-gate MOSFET with gate-S/D underlap for subthreshold operation”, IEEE Transactions on Electron Devices, 2012, vol. 59, no. 10, pp. 2846-2849.
[12] C. Jeong, D. Antoniadis, and M.S. Lundstrom, “On backscattering and mobility in nanoscale silicon MOSFETs”, IEEE Transactions on Electron Devices, vol.
56, no. 11, pp. 2762-2769, 2009.
[13] O.C. Yee and W.P. Voon, “A flexibility and accuracy comparison study of different current-voltage equations for double-gate nano-MOSFET by simulation and theory”, Applications of Modelling and Simulation, vol. 5, pp. 200-206, 2021.
[14] O.C. Yee and L.S. King, “Temperature variation effects in nano-MOSFETs based on simulation study”, International Journal of Education and Research, vol. 1, no. 2, pp. 142-158, 2013.
[15] A. Boudjella, K.C. Shiun, O.C. Yee, and L.C. Heong,
“Conception of integrated hybrid technology: CMOS- molecular electronic”, in 2008 International Conference on Electronic Design, 2008, pp. 1-4.
[16] O.C. Yee and L.S. King, “Simulation study of 2D electron density in primed and unprimed subband thin- body double-gate nano-MOSFET of three different thicknesses and two temperature states”, International
Journal of Nanoelectronics and Materials, vol. 9, no. 1, pp. 67-84, 2016.
[17] O.C. Yee and L.S. King, “Simulation study on the electrical performance of equilibrium thin-body double-gate nano-MOSFET”, Jurnal Teknologi, vol. 76, no. 1, pp. 87-95, 2015.
[18] O.C. Yee and L.S. King, “A comparison simulation study of double-gate MOSFET at 45 nm and double gate nano-MOSFET at 10 nm”, International Journal of Advanced Electrical and Electronics Engineering (IJAEEE), vol. 3, no. 3, pp. 17-19, 2014.
[19] O.C. Yee and L.S. King, “Nano-MOSFETs implementation of different logic families of two inputs NAND gate transistor level circuits: a simulation study”, Jurnal Teknologi, vol. 79, no. 7, pp. 41-49, 2017
[20] O.C. Yee and L.S. King, “A comparative study of quantum gates and classical logic gates implemented using solid-state double-gate nano-MOSFETs”, International Journal of Nanoelectronics and Materials, vol. 9, pp.
123-132, 2016.
[21] O.C. Yee and L.S. King, “Study of timing characteristics of NOT gate transistor level circuit implemented using nano-MOSFET by analyzing sub-band potential energy profile and current-voltage characteristic of quasi- ballistic transport”, World Journal of Nano Science and Engineering, vol. 6, no. 4, pp. 177-188, 2016.
[22] O.C. Yee, “Device-circuit level simulation study of three inputs complex logic gate designed using nano- MOSFETs”, Applications of Modelling and Simulation, vol.
3, no. 1, pp. 1-10, 2019.
[23] O.C. Yee, M.K. Ming, and W.P. Voon, “Device and circuit level simulation study of NOR gate logic families designed using nano-MOSFETs”, Platform: A Journal of Science and Technology, vol. 4, no. 1, pp. 73-84, 2021.
[24] O.C. Yee and L.S. King, “Simulation study on different logic families of NOT gate transistor level circuits implemented using nano-MOSFETs”, Journal of Telecommunication, Electronic and Computer Engineering (JTEC), vol. 8, no. 5, pp. 61-67, 2016.
[25] R. Clerc and G. Ghibaudo, “Analytical models and electrical characterization of advanced MOSFETs in the quasi ballistic regime”, International Journal of High-Speed Electronics and Systems, World Scientific Publishing, 2013.
[26] H. Jiang, S. Shao, W.Cai, and P. Zhang, “Boundary treatments in non-equilibrium Green’s function (NEGF) methods for quantum transport in nano-MOSFETs”, Journal of Computational Physics, vol. 227, no. 13, pp.
6533-6573, 2008.
[27] J.P. Darling and I.D. Mayergoyz, “Parallel algorithm for the solution of nonlinear Poisson equation of semiconductor device theory and its implementation on the IVIPP”, Journal of Parallel and Distributed Computing, vol. 8, no. 2, pp. 161-168, 1990.
[28] A. Khakifirooz, “Transport enhancement techniques for nanoscale MOSFETs”, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 2008.
[29] V.K. Khanna, “Physics of carrier-transport mechanisms and ultra-small scale phenomena for theoretical modelling of nanometer MOS transistors from diffusive to ballistic regimes of operation”, Physics Reports, vol.
398, pp. 67-131, 2004.
[30] OC. Yee, “Device and transistor level circuit performance analysis of nanoscale MOSFET”, Ph.D. Dissertation, Lee Kong Chain Faculty of Engineering and Science, Universiti Tunku Abdul Rahman, Malaysia, 2019.
[31] Xufeng Wang, “Nanomos 4.0: a tool to explore ultimate Si transistors and beyond”, Master of Science Dissertation, Purdue University, 2010.
[32] Zhibin Ren, “Nanoscale MOSFETs: physics, simulation and design”, Ph.D. Dissertation, Purdue University, 2001.