AHMAD ZAINOLDIAR BIN KHALIDI
SCHOOL OF MICROELECTRONIC ENGINEERING UNIVERSITI MALAYSIA PERLIS
2007
STABLE 2 STAGE CMOS AMPLIFIER
by
AHMAD ZAINOLDIAR BIN KHALIDI
Report submitted in partial fulfillment of the requirements for the degree of Bachelor of Engineering with Honours
(Electronic Engineering)
APRIL 2007
ACKNOWLEDGMENT
I would like to express my gratitude upon University Malaysia Perlis for giving me the chance to do my final year project here. My deeply gratitude to my supervisor, Puan Norhawati Binti Ahmad, lecturer School Microelectronics. Thank you so much for your help and cooperation during my project period here.
I also would like to thank a million to UniMAP, especially to the School of Microelectronics for giving me support before, during and after my project period. Special thanks to Mr. Razaidi Bin Hussin and Mrs Faizah Binti Abu Bakar and all staffs in the School of Microelectronics. I really appreciate your helpfulness and cooperation.
Thank you so much to my beloved parents, and family for your kind understanding and your moral support. Not to forget, to all my friends, thank you so much your support and never ending help.
APPROVAL AND DECLARATION SHEET
This project report titled Stable 2 Stage CMOS Amplifier was prepared and submitted by Ahmad Zainodiar Bin Khalidi (Matrix Number: 041030037) and has been found satisfactory in terms of scope, quality and presentation as partial fulfillment of the requirement for the Bachelor of Engineering ( Electronic Engineering ) in University Malaysia Perlis (UNIMAP).
Checked and Approved by
_______________________
(MRS NORHAWATI BINTI AHMAD) Project Supervisor
School of Microelectronic Engineering University Malaysia Perlis
March 2007
TABLE OF CONTENTS
Acknowledgments iii
Approval and Declaration Sheet iv
Table of Contents v
List of Tables viii
List of Figures ix
List of Abbreviations x
Abstrak xi
Abstract xii
Chapter 1 Introduction
1.1 Introduction 1
1.2 Project Background 2
1.3 Objective 3
1.4 Scope of Study 3
Chapter 2 Literature Review
2.1 Introduction 4
2.2 First Stage for the 2 stage amplifier 5
2.3 Second Stage for the 2 stage amplifier 7
2.4 Two-stage CMOS Amplifier 8
2.5 Current mirrors 9
2.6 Wilson Current mirror 12
2.7 Source Follower 13
2.8 Cascode Stage 14
2.9 Folded Cascoded 17
2.10 Differential Amplifier 18
2.11 Layout Design Rules 19
2.12 Design Rule Background 20
2.12.1 Well Rules 20
2.12.2 Transistor Rules 20
2.12.3 Contact Rules 21
2.12.4 Metal Rules 22
2.12.5 Via Rules 23
2.12.6 Other Rules 23
Chapter 3 Methodology
3.1 Circuit Description 24
3.2 Schematic Design 25
3.3 Simulation using Tsmc 0.35 26
3.4 Circuit Designing Tools 26
3.5 Layout IC station Software 27
3.6 Design Specification for Project 28
3.7 Design Specification for Gain 29
3.8 Design Specification for Slew Rate and current at 2nd Stage 32
Chapter 4 Results and Discussion
4.1 Output Waveform 34
4.2 Layout Result 36
4.3 LVS Result 37
4.4 DRC Result 38
Chapter 5 Conclusion
5.1 Summary 39
5.2 Recommendation for Future Project 40
5.3 Commercialization Potential 41
Bibliography 42
Appendix A : Mosis Design Rules 45
Appendix B : Schematic Diagram 48
Appendix C : Netlist Schematic and Netlist Layout 49
Appendix D : Flow Chart Methodology 51
Appendix E : Layout 52
Appendix F : Result LVS 53
LIST OF TABLES
Table No. Title Page
5.1 Summary of amplifier performance 39
LIST OF FIGURES
Figure No. Title Page
2.1 Two-stage amplifiers 4
2.2(a) Block diagram of 2 stage amplifier 5
2.2(b) First stage amplifier 6
2.3(a) 2 stage amplifier 7
2.3(b) Basic configuration for 2 stage amplifier 7 2.4 A CMOS realization of 2 stage amplifier 8 2.5(a) Definition of current by resistive divider 9 2.5(b) Conceptual means of copying current 10
2.5(c) Basic current mirror 10
2.6 Wilson current mirrors 12
2.7 Source followers 13
2.8(a) Cascode stage 14
2.8(b) Allowable voltage in cascode 15
2.8(c) Large signal behavior of cascode stage 15
2.9(a) Folded cascoded 17
2.9(b) Folded cascoded 17
2.10(a) Single ended circuit 18
2.10(b) Differential circuit 19
2.122 CMOS n-well process transistor and well/substrate contact cons. 21
3.2 Substrate contact 22
4.1(a) Show Cload = 10pF 34
4.1(b) Show Cload = 1nF 35
4.1(c) Trade-off in analog design 36
4.2 Schematic diagram without input signal 36
4.3 LVS result 37
4.4 DRC result 38
LIST OF ABBREVIATIONS
IC Integrated Circuit
VLSI Very Large Scale Integration
µ Mobility of charge
L Effective channel length
W/L Aspect ratio
VTH Voltage threshold
Cox Total capacitance per unit length
gm Transconductance
2 PERINGKAT CMOS PENGUAT STABIL
ABSTRAK
Dalam beberapa tahun kebelakangan ini, telah ada satu usaha bagi menghasilkan produk berasaskan teknologi peralatan. Komponen kritikal yang diusahakan dalam system ini adalah sebuah penguat. Reka bentuk 2 peringkst penguat merupakan langkah yang digerak kerjakan bagi mendapatkan keluaran yang stabil apabila diberikan beban kapasitif yang berbeza. Projek ini dijalankan dengan menggunakan topologi penyelarian. Teknik ini digunakan untuk mengoptimakan keberkesanan penguat itu khususnya offset voltan dan litar biasing. Litar ini menggunakan teknologi 0.35µ dengan penggunaan arus sebanyak 110µA. Perencanaan projek ini telah menggunakan perisian Mentor Graphic bagi menguji dan merekabentuk layout. Untuk perencanaan reka bentuk layout, teknologi TSMC telah digunakan. Menggunakan penyelarian bagi mengoptimakan litar, penguat fasa boleh dikawal. Di dalam perlaksanaan CMOS penguat, terdapat batas-batas kemampuan penguat yang terhad kepada voltan keluaran tinggi dan offset voltan. Voltan yang terhasil daripada perlaksaan ini dijangka menghasilkan keluaran yang stabil.
ABSTRACT
In the last few years there has been an effort to integrate electrochemical instrumentation. A critical component of such a system is an amplifier. These projects design a “Stable Two stage CMOS amplifier”. This is achieved through the use of an optimized cascaded compensation topology. A new shifting technique allows independent optimization of drive capability, noise and systematic offset voltage. The circuit is in a 0.35µm technology and has a quiescent current consumption of 110µA. This designing currently using Mentor Graphic software to test the schematic and also to design the layout.
The design layout is designed using rules from TSMC. Using cascoded compensation with optimized circuit parameters, the worst case phase margin of the amplifier can be controlled to acceptable values. In two stage CMOS amplifier, there is usually a tradeoff aware high output drive capability and low systematic offset voltage. The output voltage that expects to get must in stable conditional and the bias current setting according to the calculation estimation.
