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Nonvolatile Ferroelectric-Domain-Wall Memory Embedded in a Complex Topological Domain Structure

Wenda Yang, Guo Tian, Hua Fan, Yue Zhao, Hongying Chen, Luyong Zhang,* Yadong Wang, Zhen Fan, Zhipeng Hou, Deyang Chen, Jinwei Gao, Min Zeng,* Xubing Lu, Minghui Qin, Xingsen Gao, and Jun-Ming Liu*

W. Yang, G. Tian, H. Chen, L. Zhang, Y. Wang, Z. Fan, Z. Hou, D. Chen, J. Gao, M. Zeng, X. Lu, M. Qin, X. Gao

Guangdong Provincial Key Laboratory of Quantum Engineering and Quantum Materials

Institute for Advanced Materials

South China Academy of Advanced Optoelectronics South China Normal University

Guangzhou 510006, China

E-mail: [email protected]; [email protected];

[email protected] H. Fan, Y. Zhao

The Department of Physics

Southern University of Science and Technology Shenzhen 518000, China

J.-M. Liu

Laboratory of Solid-State Microstructures Nanjing University

Nanjing 210093, China

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adma.202107711.

DOI: 10.1002/adma.202107711

1. Introduction

Ferroelectric domain walls, a type of tun- able atomic sharp homo-interface, have attracted widespread attention as an arena for exploring a wide range of emerging physical properties (e.g., enhanced conductivity, giant photovoltages, and magne- toresistance) as well due to their immense application potential.^[1–8] For instance, highly conductive charged domain walls (CDWs) have been discovered in numerous originally insulating ferroelectric materials, such as BiFeO₃ (BFO),^[9,10] BaTiO₃,^[11]

Pb(Zr,Ti)O3,^[12] LiNbO3,^[13] and YMnO3.^[14]

These atomically sharp conductive channels can be created, eliminated, or dis- placed by external stimuli, constituting the basis of various energy-efficient and config- urable nanoelectronic devices (i.e., domain- wall electronics), including nonvolatile memories^[15–18] and memristors.^[19] More- over, these wall devices have the potential to be scaled down to ultrasmall dimensions, mainly because of the atomically sharp nature of the conductive domain walls.^[18]

Recent studies describe some prototypes of domain-wall electronic devices (e.g., memories) based on the nonvolatile creation and erasure of CDWs and nondestructive current readout.^[15–19]

However, such devices usually face the obstacle of an unstable restoration process because of difficulties with regards to the deterministic manipulation of the conduction channels in the domain walls.^[10,16] For instance, a CDW unit might not appear at the same location after an erasure and rewriting cycle, owing to the complexities of domain switching.^[20] Moreover, the conductivity of a CDW unit may be greatly modulated by local distortions (e.g., bending) or defects, which adds to the difficulty of deterministically controlling the domain-wall conduction states.^[21]

In recent years, there has been a rapid development in dis- covering exotic topological domain textures (e.g., flux-closure quadrant vortex, vortex, skyrmion, and center-type quadrant domain states),^[22–34] likely offering new opportunities for the deterministic manipulation of domain-wall conduction. For instance, reversible switching between two stable conduction states was realized by using CDWs confined in center-type quadrant domains in BFO nanoislands or nanoplates, whereby The discovery and precise manipulation of atomic-size conductive ferroelec-

tric domain walls offers new opportunities for a wide range of prospective electronic devices, and the emerging field of walltronics. Herein, a highly stable and fatigue-resistant nonvolatile memory device is demonstrated, which is based on deterministic creation and erasure of conductive domain walls that are geometrically confined in a topological domain structure. By introducing a pair of delicately designed coaxial electrodes onto the epitaxial BiFeO₃ film, a center-type quadrant topological domain with conductive charged domain walls can be easily created. More importantly, reversible switching of the quadrant domain between the convergent state with highly conductive confined walls and the divergent state with insulating confined walls can be realized, resulting in an apparent resistance change with a large on/off ratio of >10⁴ and a technically preferred readout current (up to 40 nA).

Owing to restrictions from the clamped quadrant ferroelastic domain, the device exhibits excellent restoration repeatability over 10⁸ cycles and a long retention of over 12 days (>10⁶ s). These results provide a new pathway toward high-performance ferroelectric-domain-wall memory, which may spur extensive interest in exploring the immense potential in the emerging field of walltronics.

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the switching path of the CDWs was “protected” by the clamped ferroelastic quad-domain and geometric restriction effects.^[29–31]

More recently, robust electrically programmable quasi-1D conduction channels were realized in the cores of quadrant centers or vortex states confined in BFO nanoislands.^[32] These observations exemplify that conduction channels confined in complex topological domain structures may be highly preferable candi- dates for emerging memory devices with excellent controlla- bility and stability.

However, previous devices containing topologically confined CDWs were mainly based on bare nanoislands or nanoplates without top electrodes.^[30,31] This makes such devices less likely to be used as practical memory devices, and also raises the question of whether the controllable topological domain states and CDWs can still be maintained after adding top electrodes because the electrostatic boundary condition is changed. In addition, only some basic functionalities (e.g., writing/erasing, reading) have been demonstrated for previous devices, while the performance metrics critical for practical use, such as long-term stability and high restoration repeatability, have yet to be demonstrated. An equally important but much less-frequently addressed technical issue was the low readout current level of previous devices.

In many cases, the readout current was rather small (≈1 nA), and was insufficient for driving a high-speed readout circuit according to the Johnson–Nyquist limit.^[10,35,36] Therefore, the development of an alternative strategy for overcoming or avoiding these obstacles is of great interest.

One of the best strategies, if applicable, is to fabricate devices directly from well-prepared thin films, allowing for an integration with advanced microelectronic technologies.

For example, one may design an electrode-patterned unit that creates an electric field distribution that is favorable for the formation of well-defined CDWs confined in quadrant domains. Herein, we demonstrate a prototype domain-wall memory unit embedded in a center-type quadrant topological domain structure (see Figure 1a). These structures were generated via a delicately designed coplanar electrode geometry on well-prepared BFO thin films, as presented in the Exper- imental Section. The as-generated center-type quadrant domains can be easily created and switched back and forth between the divergent state, which contains poorly conductive tail-to-tail CDWs (T–T CDWs), and the convergent state, which contains highly conductive head-to-head CDWs (H–H CDWs), leading to a well-defined resistive-switching memory behavior. Such a memory unit demonstrates good, repeatable resistive-switching behavior with a high on/off ratio (10⁴), as well as a large readout current of up to 40 nA, which is the preferred value for a reliable reading operation. Furthermore, owing to the restrictions of the specific ferroelastic quadrant domain structure, the device exhibits a long retention (up to 10⁶ s in the test) and high endurance (up to 10⁸ cycles, the largest tested cycles), providing a new pathway toward high- performance domain-wall memories that can easily be scaled down and integrated.

Figure 1. Creation of center-type quadrant domains. a) Schematic diagram of the device structure. It is noted that the bias voltage was applied to the Au electrode and that the tip was grounded in all figures. b) Schematic illustrations of radial electric fields on circular exposed BFO region generated by applying an electric bias between the tip and the Au electrodes. c,d) The convergent and divergent domain states of the created quadrant center along with their corresponding domain-wall conduction states: vector PFM images and corresponding in-plane polarization vector maps, as well as CAFM maps for both center convergent (c) and divergent states (d), which were obtained after applying tip biases of +6.0 and −6.0 V, respectively. To construct the in-plane vector maps, lateral PFM amplitude (L-Amp) and phase (L-Pha) were recorded for sample rotations of 0° and 90°.

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2. Results and Discussion

2.1. Creation of Center-Type Quadrant Domains

Epitaxial BFO thin films were deposited onto (001)-oriented SrTiO₃ (STO) substrates using pulsed laser deposition (PLD).

All as-grown BFO films exhibit a mosaic domain structure, which is a prerequisite and will be further utilized for creating quadrant center domains containing conductive CDWs (details of the preparation are given in the Experimental Section). The rhombohedral BFO phase and its epitaxy were demonstrated by X-ray diffraction (XRD) and reciprocal space mapping (RSM) (see Figure S1, Supporting Information). To fabricate the device, an Au layer was first deposited onto the BFO film surface via thermal evaporation, and then, an array of circularly shaped regions was scratched away from the Au film using an atomic force microscopy (AFM) tip via AFM lithography. Thus, an array of circularly exposed BFO regions surrounded by circular Au electrodes was developed (see Figure 1a). The fabrication details can be found in the Experimental Section and in Figure S2, Supporting Information. It should be mentioned that the as-exposed BFO regions exhibit piezoelectric properties similar to those of the as-prepared thin films with mosaic domains (see Figure S3, Supporting Information).

Such well-fabricated circular patterns then enable the creation of center quadrant domains with the assistance of a conductive AFM (C-AFM) tip. In sequence, by placing a stationary C-AFM tip onto the center of a circularly exposed BFO region, the tip and the surrounding Au electrode form a coaxial electrode pair, which can generate a radially distributed electric field in the exposed BFO region (see Figure 1b). This is expected to radially align the in-plane ferroelectric polarization, so that a center-type quadrant domain, as restricted by the BFO crystal symmetry, can be generated after removal of the electric field.

It should be mentioned that such a quadrant domain is highly robust once it has been generated at room temperature (25 °C).

To determine the local domain structure of the circularly exposed region, vector piezoresponse force microscopy (PFM) was conducted with a sample rotation of 0° and 90°

(in fact, at many angles) with respect to a reference axis, following a method described previously.^[28,32] This can be used to largely determine the projection of the local polarization vectors along the [001], [010], and [100] axes of the BFO lattice.

The out-of-plane (vertical) and in-plane (lateral) PFM images are shown in Figure 1c,d and illustrate the created domain structures and corresponding current maps probed by applied electric fields of ±6.0 V between the tip and the surrounding Au electrode. For more details, the bright and dark contrasts in the lateral PFM images indicate opposite polarization components perpendicular to the cantilever direction. Given that the BFO crystal symmetry allows only eight possible [111] polarization directions, we can qualitatively reconstruct the local distribution of the polarization structure in combi- nation with the PFM results using a MATLAB program, as shown in the in-plane projection of the local polarization vector map (see bottom row in Figure 1c,d). The in-plane vector map clearly indicates that applying an electric pulse of +6.0 V (applied to the Au electrode) is sufficient for creating a quadrant center-convergent domain pattern (with upward

vertical polarization), whereby all in-plane polarizations point inward to the center, and thus, cross-shaped H–H CDWs are generated. In reverse, an electric pulse of −6.0 V can produce a quadrant divergent domain, with the in-plane polarization pointing outwards from the center. Thus, cross-shaped T–T CDWs are generated.

It is also interesting to see that electric biasing can simultaneously switch the vertical polarization of an exposed BFO region, as reflected by the contrast change in the vertical PFM phase image (see the third row in Figure 1c,d). This vertical polarization switching can also be demonstrated by the typical piezoresponse hysteresis loops, based on which coercive voltages of ≈±4.8 V are revealed, analogous to those of the bare BFO film on the bottom electrode (see Figure S4, Supporting Information). The simultaneous reversal of both the in-plane and the vertical components indicates that the center domain switching is completely a 180° switching.

Subsequently, the local electric current profile can be mapped using the C-AFM mode under a sampling bias of +2.5 V. For the initial state with the mosaic domain pattern, the exposed BFO surface exhibits a very low conductive current (<1.0 pA, close to the noise level), in contrast to the highly conductive current obtained for the electrode region (see Figure S5, Sup- porting Information). After applying a bias of +6.0 V to form a center-convergent domain, one can clearly see the apparent hallmark of the cross-shaped highly conductive current pattern originating from the H–H CDW in the center-convergent state (see both Figure 1c and Figure S5, Supporting Information).

Conversely, for the center-divergent domain triggered by a +6.0 V bias voltage, the cross-shaped current pattern disappears in the corresponding C-AFM map, as the T–T CDW shows very low conductivity comparable to the domain interior. The reversible switching between the different domain-wall conduction states shows very good repeatability, which is also likely a con- sequence of the “protection” from the unique ferroelastic topological center domain.^[29,30]

This observation agrees well with previous observations of the conductive center domain state in BFO nanoislands,^[32]

while the total conduction current level in this study is one or two orders of magnitude larger (>10 nA) compared with those observed in nanoislands (≈1.0 nA).^[30–32] Such a high conductance with the H–H CDWs can be interpreted with the accu- mulation of charge carriers at the CDW with unbalanced net bound charges, which can greatly enhance the electric potential and thus attract electrons for screening the positive net bound charges. The bound charges can also bend the energy band inside the CDWs, which lowers the conduction band level below the Fermi level, thus resulting in metallic conducting behavior and a significant enhancement in conductivity.^[9,11]

This metallic conduction behavior can be further confirmed by the current–temperature (I–T) curves measured in CDWs (see Figure S6, Supporting Information). It was observed that the current decreased with increasing temperature, thereby con- firming the metallic conduction behavior.^[9,17] Unlike conven- tional CDW, which can be easily distorted by local perturbations thus losing part of its conductivity,^[21] the topologically confined CDW is rather stable with very few distortions due to the restrictions from its unique ferroelastic domains,^[30,31] which is favorable for maintaining a high conductivity.

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2.2. Resistive-Switching Properties

Based on distinguished conductance switching between the convergent and divergent center states, one can propose a prototype of a nonvolatile domain-wall memory device, and its configuration and operation are schematically shown in Figure 2a. It is noted that the C-AFM tip is fixed at the center of the exposed BFO region and serves as a central electrode, and that the bias voltage is applied to the surrounding circular Au electrode. The characteristics of this domain-wall memory are analogous to a highly repeatable resistive-switching behavior, which can be well demonstrated by quasi-static current–voltage (I–V) measurements at a sweeping bias range within ±7.0 V for 1000 switching cycles. As shown in Figure 2b, all I–V curves exhibit a symmetric hysteretic behavior. One can see that when the bias voltage increases to ≈4.5 V, the readout current suddenly jumps from a low level (<1.0 pA) to a rather high level (≈40 nA), and then increases linearly for a further increasing bias. This sudden jump in the conductive current agrees well with the formation of a highly conductive center-convergent state, which is consistent with the observation shown in Figure 1c. The onset voltages (set voltage, V_set and reset voltage, V_reset) coincide with the coercive voltages shown in Figure S4, Supporting Informa- tion. After the formation of a center-convergent state with H–H CDWs, the conductive current increases linearly, likely because of the metallic nature of the H–H CDW, as confirmed by the temperature-dependent C-AFM measurement mentioned

above. The as-created metallic channel can maintain its conductivity as the bias sweeps toward negative voltage, suggesting its nonvolatility. It is also noted that in the low bias range (within

±2.0 V) the current level becomes very small, and that the I–V curve no longer follows linear behavior, probably because of the presence of an interfacial insulating gap or wedge domain state close to the electrodes.^[9,11] Such an interfacial insulating state is also analogous to a bipolar selector for a resistance random access memory cell, which is promising for suppressing unwanted sneak current paths in a crossbar-array integrated electroresistance memory.^[37]

In addition, the resistance switching behavior, as illustrated based on the I–V curve, gives rise to a large on/off ratio of more than four orders of magnitude at a relatively low readout voltage (+2.5 V). The nonvolatile data readout is also indicated by performing minor I–V curves at a sweeping bias range of

±3.0 V, indicating a large on/off resistance ratio of over 10⁴ (see Figure 2c). More interestingly, the device exhibited highly repeatable I–V characteristics. It can be seen that the hysteretic I–V curve almost follows the same trace as in the first cycle after 1000 cycles. Moreover, we extract from Figure 2b the rela- tive distribution of the readout current (Log[I]) for both LRS and HRS recorded at a reading bias (Vr) of +2.5 V, as well as those of V_set and V_reset, as shown in Figure 2d. It can be seen that all four parameters exhibit a very narrow distribution range, con- firming the ultrahigh repeatability for good data restoration of the device. This is also exemplified by the high repeatability for

Figure 2. Resistance switching behaviors of the devices. a) Schematic working principle based on creation and erasure of conductive domain-wall states. b) Quasistatic I–V curves for 1000 consequent switching cycles at a bias range of ±7.0 V. Inset shows a semi-logarithmic I–V curve. c) I–V curves at a smaller bias range of ±3.0 V for both HRS and LRS. d) Distributions of log(current) for both LRS/HRS and switching voltages (set and reset voltages: Vset and Vreset) derived from the statistics of 10³ consecutive I–V cycles (shown in (a)). e,f) Resistive-switching characteristics for different device dimensions (i.e., diameters of the circular exposed BFO regions): I–V hysteresis curves for devices with different characteristic device dimensions between 200 and 500 nm (e), and length dependent readout currents (for two different reading biases [V_r]) and V_set extracted from the I–V curves (f).

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the conduction state switching of CDWs, indicating the important role of “protection” from the clamped ferroelastic quadrant domain, which is advantageous for high-performance nonvolatile memory with a nondestructive current readout.

Furthermore, the effect of the lateral dimensions of the devices on the resistive-switching properties was also examined, as shown in Figure S7, Supporting Information. A similar resistive-switching behavior (i.e., I–V curves) can be observed for different characteristic dimensions (i.e., the diameters of the exposed BFO regions) ranging from 200 to 500 nm, as reflected by the sharp resistance change that corresponds to the switching between convergent and divergent center states (see Figure 2e). More interestingly, dimension shrinkage can lead to an apparent reduction in the onset voltage as well as an increase in the readout current at a fixed Vr, for example, the readout current in LRS increases from 8 nA for a lateral size of 500 nm to 15 nA for 200 nm at a Vr of 2.5 V, and increases from 17 nA for 500 nm to 40 nA for 200 nm at a V_r of 4.0 V, almost following an exponential law (see Figure 2f). In practical devices, these large reading current levels are essential for a high signal-to-noise level and for driving fast operations.^[35,36]

The above observation also indicates that with dimensional downscaling, the performance of these devices can be further improved (enhancement in readout current and reduction in Vset). It was theoretically predicted that the quadrant center domain can remain stable at an ultrasmall dimension (≈16 nm),^[31] implying the huge potential of such devices for the

development of ultrahigh-density memory while maintaining good device switching characteristics.

2.3. Performance of Domain-Wall Memory Device

To further understand the memory performance of the as- generated device, we examined the memory switching window, retention, endurance, and fast switching dynamics of a randomly selected device, as shown in Figure 3. Repeated testing of other devices show similar trends, although quantitative differences may exist. The memory switching hysteresis for the selected device is shown in Figure 3a, and the data were collected using a sequence of electric pulses. The resulting conductive states were read out under a fixed Vr of 2.5 V. The readout current loop exhibits a rather square hysteresis with abrupt jumps at ≈±4.5 V, showing a well-established memory window that is analogous to its corresponding piezoresponse hysteresis loop.

In addition, the stability of the memory device is further confirmed by retention testing, as shown in Figure 3b, and the data show very stable conductive states for both the LRS and HRS over long retention durations of up to 10⁶ s (i.e., 12 days, which is the longest testing time in this work, with a much longer duration expected). This high stability was further verified by a high-temperature retention test, which demonstrates that the quadrant domain structures and the corresponding resistance

Figure 3. Performance of the devices. a) Readout current versus pulse voltage obtained after applying different write pulses (at a fixed reading bias of 2.5 V), indicating the memory switching window. b,c) The retention properties for LRS and HRS at a room temperature of 25 °C (b) and at an elevated temperature of 150 °C (c). d) Endurance properties for both LRS and HRS over 10⁸ switching cycles using the square-pulsed waveform (pulse width of 1.0 µs and maximum voltage of ±8.0 V). e) Evolutions of readout current with respect to pulse duration under different pulse voltages. f) Relationship between switching time and switching voltage (VS) extracted from (e), indicating a minimum switching time of 120 ns at a pulse voltage of +9.0 V.

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states can maintain rather good stability at a temperature of 150 °C for 10⁴ s, except for some slight variations in the HRS (see Figure 3c and Figure S6a, Supporting Information). These observations indicate the good long-term stability of the device and good data retention against thermal perturbations, which is an advantageous feature for device applications.

Another important aspect of memory performance is the endurance property, which reflects the repeatability of the data restoration operation. As shown in Figure 3d, the device is subjected to a set of reversible switching voltage (V_S) pulses (±8.0 V with pulse width of 1.0 µs) for up to 10⁸ cycles, and the conductive levels of the LRS and HRS are recorded at several inter- vals. It was found that the device can maintain its well-established resistance switching functionality during fatigue testing, wherein the readout current of the LRS and HRS showed a very small variation for up to 10⁸ switching cycles (see Figure 3d and Figure S8, Supporting Information), indicating a good fatigue resistant behavior. This agrees well with the high repeatability of the I–V curves shown in Figure 2b.

To provide a more comprehensive understanding of the memory performance, it is essential to understand the switching dynamic behaviors of the conduction states. Figure 3e shows the fast-switching dynamics under varying electric pulses V_S, wherein a constant V_r ≈ 2.5 V is used to read out the different resistance states (see Experimental Section). It can be seen that in addition to the resistance state switches from HRS to LRS, the readout current exhibits a fairly abrupt jump at a characteristic time. As the switching dynamic behaviors of the conduction state are closely related to the polarization switching behaviors, the jump in the conduction state can also reflect a sudden domain switching time (t0). This implies a very

short growth time for the reversed domain initiated from very few nucleation sites,^[18] which may not conform to the typical Kolmogorov–Avrami–Ishibashi relation, which usually involves a rather broad distribution of the domain switching time.^[38,39]

It can also be observed from Figure 3e, as VS increases, t₀ shows a quick reduction. The extracted t₀ − 1/VS curve is shown in a semilogarithmic form in Figure 3f, which fits well to the Merz law of t₀ = τ0exp[(E_a/E)μ],^[40,41] where τ0 is the switching time in an infinite electric field, Ea is the activation field determined to be 22.4 MV cm⁻¹, and μ is the corrected component determined to be 1. It is noted that the abrupt tran- sition from HRS to LRS persists as V_S decreases from +9.0 to +6.0 V, which is unlike a typical polarization switching behavior, which often shows a gradual switching process at low applied voltages.

2.4. Individually Writing and Reading Data Bits in a Device Array Moreover, the ability of controlled writing and erasing operations in a 3 × 3 device array is shown in Figure 4a. The exposed BFO regions in all devices show a uniform low conductivity in the initial state, which can also be considered as HRS. After applying a bias voltage of +6.0 V on eight selected devices (except one for reference), one can clearly see that cross-shaped current patterns appear in the selected BFO regions in the C-AFM image, reflecting the formation of center-convergent domains and LRS. Subsequently, five of the written memory units framed by the black dashed line are erased by applying a bias of −6.0 V. The cross-shaped current disappears in all five devices, suggesting the conversion from LRS to HRS and the

Figure 4. Writing and erasing of individual data bits in a device array and schematic conceptual crossbar integrated devices. a) Individual writing and erasing of data bits in a 3 × 3 device array. Here, the Au layer is grounded, and the AFM tip acts as a movable electrode to address the individual device with a ±6.0 V bias voltage. b) Conceptual crossbar-integrated domain-wall memory device. c,d) Example of a device array connected by word lines fabricated by the EBL technique: topographic image (c), as well as CAFM and PFM images illustrating the capability of individual data reading, and repeatable writing and erasing process (d).

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formation of low conductive T–T CDWs. The corresponding PFM images for the devices subjected to different bias voltages are shown in Figure S9, Supporting Information, which verifies the manipulation of individual quadrant domain states in the respective devices, in accordance with changes in the conduction states. These results demonstrate the capability of individual data addressing, programmable writing and reading, limited crosstalk between neighboring cells, and good uni- formity of the devices, which make them promising for imple- mentation in memory devices with nondestructive current readout.

In practical memory devices, these functionalities should be implemented using bit lines and word lines. Therefore, we proposed a conceptual crossbar structure for memory devices, as illustrated in Figure 4b. A single memory unit consists of a central electrode/circular BFO area/surrounding electrode structure, whereby the two electrodes are attached to bit and word lines, respectively. Such a device architecture with a high integration density enables data writing and reading operations for any randomly selected individual device unit from its corresponding set of word and bit lines. To elaborate the feasibility of this scheme, we also fabricated an array of ring-shaped electrodes with word lines by using the electron beam lithography (EBL) technique (see Experimental Section), which further demonstrates the ability of individual data reading, as well as repeatable writing and erasing cycles (see Figure 4c,d).

It is also worth mentioning that a real integrated crossbar memory usually involves an unwanted cross-talk issue from bit/word lines, for example, the sneak-path problem, which may lead to unintended switching or reading signal errors.^[37]

In our case, every memory cell in the array shows a very small current in the low bias voltage range (shown in Figure 2b), like carrying an embedded bipolar selector, which could be helpful for suppressing the unwanted sneak current path through the neighboring LRS cells.^[37] At the present stage, we are still unable to directly evaluate the crosstalk effects experimentally, and more efforts are needed to further understand this issue.

The above results reflect the promising possibility of developing high-density domain-wall memories that exhibit fatigue resistance, long-term retention, and low energy consumption properties. Moreover, the device array structure is compatible with large-area fabrication techniques. For instance, we have successfully fabricated a large-area device array via a nanosphere lithography technique, and the as-fabricated devices also showed similar memory functionalities as the devices described above (see Figure S10, Supporting Information). These ben- eficial features also provide a new paradigm for developing new concept nanoelectronic devices based on programmable functional domain walls confined in topological ferroelastic domains, which may spur more efforts to explore the immense application potentials of ferroelectric domain-wall electronics.

3. Conclusion

We have successfully fabricated well-designed and high-performance memory devices based on conductive domain walls confined in center-type topological quadrant domains produced in high-quality epitaxial BFO films. By using a pair of delicately

designed co-axial electrodes, one can deterministically create and reversibly switch the quadrant domains, leading to a sharp switch between distinct domain-wall conduction states. This can be implemented in nonvolatile memory devices that allow for a nondestructive current readout of different domain-wall conduction states, with a large on/off resistance ratio of over 10⁴ and a high readout current. Moreover, owing to the “protection” from the clamped topological ferroelastic quadrant domains, the devices exhibited a long retention time of 10⁶ s and a high fatigue resistance of hundred million switching cycles. The devices also showed good compatibility with high- density integration crossbar arrays, which provides a new paradigm for developing domain-wall electronic devices.

4. Experimental Section

Fabrication of the Devices: The BFO thin film was deposited onto a (001)-oriented SrTiO₃ substrate by PLD using a KrF excimer laser (wavelength λ = 248 nm) at a substrate temperature of 660 °C under an oxygen atmosphere of 6 Pa. The laser pulse energy was 300 mJ, with a repetition rate of 8 Hz. Then, an Au layer with a thickness of 10 nm was deposited onto the BFO film surface via thermal evaporation. To fabricate the device, the AFM tip was used to scratch a circular Au region with a constant tip pressure of 40 µN and a velocity of 1.0 µm s⁻¹, as schematically illustrated in Figure S2, Supporting Information.

Consequently, a circular exposed region of the BFO film surrounded by the Au electrode was formed. Moreover, such devices could also be fabricated via an EBL technique on a layer of polymethyl methacrylate resist or a nanosphere lithography method using an orderly arranged polymethyl nanosphere template, which was then followed by the deposition of an Au layer and a final lift-off process.

Microstructural Characterizations: The epitaxial structures of the BFO film were characterized by XRD (PANalytical XPert PRO), including θ–2θ scanning and RSM along the (203) diffraction spot. The topography images were obtained using AFM (Cypher, Asylum Research).

Piezoresponse Force Microscopy and Conductive Atomic Force Microscopy Characterizations: The ferroelectric domain structures of the devices were characterized by PFM (Cypher, Asylum Research) using conductive PFM probes (Arrow EFM, Nanoworld). Local piezoresponse loop measurements were carried out by fixing the PFM probe on a randomly selected BFO region and then applying a triangular square waveform accompanied by a small AC driving voltage from the probe. Using the vector PFM mode, one could simultaneously map the vertical and lateral piezoresponse signals of the exposed BFO area. To determine the domain structures, both the vertical and lateral PFM images were recorded at sample rotation angles of 0° and 90°. The current distribution maps were characterized by C-AFM using conductive probes (HA_HR_DCP, TipNano).

Electrical Characterization: The I–V curves were measured using a precise current meter (Keithley 6430) in the voltage-sweep mode, which was connected to the C-AFM tip that was fixed on the center of an exposed BFO region and serving as a stationary electrode. The memory performance tests were conducted in the C-AFM mode, wherein a sequence of electric pulses with triangular variational amplitudes were applied to the Au layer to trigger domain switching with a pulse width of 5.0 ms. Immediately after each pulse, the conduction state was read by using a fixed reading bias (V_r) of 2.5 V. For endurance testing, we applied reversible electric pulses (with a square pulse width of 1.0 µs, and a maximum voltage of ±8.0 V) for up to 10⁸ switching cycles. To determine the resistive-switching time, they applied square electric pulses (V_s) for varying durations by using a pulse generator (Agilent 33250A), and then recorded the conduction state using a precision current meter (Keithley 6430) at a read bias of +2.5 V after each pulse. The switching time was determined to be the pulse duration during which the resistive change from HRS to LRS was completed. It was also noted that to access the

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small device, both the pulse generator and the precision current meter were connected to the C-AFM tip.

Supporting Information

Supporting Information is available from the Wiley Online Library or from the author.

Acknowledgements

The authors would like to acknowledge the financial support from the National Natural Science Foundation of China (Grant Nos.

92163210, 11674108, 52002134), the Science and Technology Program of Guangzhou (No. 2019050001), the project for Basic and Applied Basic research Foundation of Guangdong Province (No. 2019A1515110707), the Science and Technology Planning Project of Guangdong Province (No.

2019KQNCX028), and the Natural Science Foundation of South China Normal University (No. 19KJ01).

Conflict of Interest

The authors declare no conflict of interest.

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.

Keywords

domain-wall memory, ferroelectric domain walls, polar topological domains

Received: September 26, 2021 Revised: December 18, 2021 Published online:

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