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From Unipolar, WORM-Type to Ambipolar, Bistable

Organic Electret Memory Device by Controlling Minority Lateral Transport

Waner He, Wenchao Xu, Huixin He, Xiaosai Jing, Chuan Liu,* Jiajun Feng, Chunlai Luo, Zhen Fan, Sujuan Wu, Jinwei Gao, Guofu Zhou, Xubing Lu,* and Junming Liu

DOI: 10.1002/aelm.201901320

1. Introduction

Organic nonvolatile memory devices have attracted increasing attention in both aca- demia and industry due to their numerous advantages for application in charge storage media, including light weight, low cost, and flexibility.^[1–3] Polymer electret memory (PEM) devices based on organic thin-film transistors (OTFTs) are an impor- tant type of organic nonvolatile memory devices in which memory arises from field- effect modulation via efficient charge injec- tion in chargeable polymer gate electrets.

The development of high-performance PEM devices has attracted considerable interest because of their simple fabrication process and good repeatability.^[4–9]

Previous studies have shown that the memory window depends strongly on the polarity, conjugation length, and architec- ture of polymer electrets.^[10–12] For instance, photosensitive elec- tret materials have been reported by Jeong et al.^[13] and glucose- based oligosaccharides or polysaccharides as green materials have been reported by Chen’s group.^[14] Also, novel blocking oxide materials have been investigated. Yeh et al.^[15] reported low-operation-voltage (<20 V) memory devices based on high- permittivity (high-k) HfO₂ blocking oxides and polymer electret layers. They found that the trapped charge begins to seriously degrade after only 10³ s. Nam et al.^[7] reported a memory device with a very low-operation voltage (5 V) based on the high-k polymer poly(vinyl alcohol), which was used as both a blocking oxide and a charge trapping layer. But the programming/

erasing (P/E) pulse width for this device was relatively long (3 s). Despite the significant progress in PEM devices,^[10–18]

simultaneously achieving high speed, high reliability, and low- operation voltage in PEM devices still remains challenging.

The underlying device physics related to P/E processes and charge trapping mechanisms remain unclear or under debate.[11,14,19–21] For instance, memory devices based on uni- polar organic semiconductor pentacene as the active layer exhibit bipolar memory characteristics.^[19] Li et al.^[20] fabricated a poly(methyl methacrylate)–OTFT memory device with a p-type pentacene channel that only exhibited trapping and de- trapping of minority electrons. Chiu^[21] reported the trapping of minority holes in an n-type semiconductor-based memory Write-once-read-many (WORM) memory behavior is often observed in

polymer electret memory (PEM) devices, greatly limiting their overall per- formance. This paper systematically investigates the device physics of PEM devices with poly(α-methylstyrene) as a charge trapping layer and pentacene as a semiconductor channel. The combined experiments on transistors, capacitances, and optical spectroscopy reveal that both the WORM memory behavior after negative and positive pulses and the gradual formation of memory after the continuous scanning are the results of the deficiency in minority (electrons) transport and trapping. Corresponding quantitative models are established and well explain the two-stage, gradual trapping processes to form memory. By reducing the structural disorder and lateral channel length, ambipolar, bistable memory and much faster formation of memory window is obtained based on the same PEM device. The insights into device physics of PEM devices are expected to facilitate the design of organic, nonvolatile memory devices with high programming and erasing efficiencies.

W.-E. He, W.-C. Xu, H.-X. He, X.-S. Jing, C.-L. Luo, Prof. Z. Fan, Prof. S.-J. Wu, Prof. J.-W. Gao, Prof. X.-B. Lu

Institute for Advanced Materials and Guangdong Provincial Key Laboratory of Optical Information Materials and Technology South China Academy of Advanced Optoelectronics

South China Normal University Guangzhou 510006, China E-mail: luxubing@m.scnu.edu.cn Prof. C. Liu

State Key Laboratory of Optoelectronic Materials and Technologies School of Electronics and Information Technology

Sun Yat-Sen University Guangzhou 510274, China E-mail: liuchuan5@mail.sysu.edu.cn J.-J. Feng, Prof. J.-M. Liu

Laboratory of Solid-State Microstructures and Innovation Center of Advanced Microstructures

Nanjing University Nanjing 21009, China Prof. G.-F. Zhou

Institute of Electronic Paper Displays and Guangdong Provincial Key Laboratory of Optical Information Materials and Technology South China Academy of Advanced Optoelectronics South China Normal University

Guangzhou 510006, China

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/aelm.201901320.

device. Furthermore, some PEM devices even show write-once- read-many (WORM) type memory behaviors.^[11,14] Among the investigated PEM devices, unipolar WORM-type memory is a kind of nonvolatile memory which can only achieve unidi- rectional programing, and cannot be realized simultaneously with both the programming and erasing states.^[22–24] Important questions have been raised from the above experimental phe- nomena, but have not been understood due to lack of systematic studies on the trapping procedures. For instance, why do some devices show unipolar memory effect? How to change unipolar memory PEM device into ambipolar, bistable memory device?

Why do some devices need large programming voltage or long programming time and how to improve the performance?

Herein, OTFT memory devices based on pentacene as a typical channel material and poly(α-methylstyrene) (PαMS) as a charge trapping material are studied. The characteristics after negative or positive bias, including pulse or continuous scan- ning, were investigated to reveal the different impact of elec- tron and hole trapping in the WORM-type memory. Then, the dynamic process of minority (electron) trapping is studied in TFT structure and metal–insulator–semiconductor (MIS) struc- ture, revealing the different role of lateral transport and ver- tical injection. Corresponding mechanisms are proposed and quantitative models are established that well explain the trap- ping behaviors. Finally, based on the physical understanding, optimized devices were obtained that show ambipolar, bistable memory. The studies develop understanding and interpretation of the WORM memory characteristics and provide strategies to optimize OTFT-based memory devices.

2. Results and Discussion

2.1. Typical Memory Characteristics

Figure 1a shows a schematic diagram of the cross-sectional structure of the bottom gate/top contact OTFT-based PEM

device used in this work, in which the PαMS was adopted as charge-trapping layer. As shown in Figure S1 of the Supporting Information, the atomic force microscopy (AFM) surface mor- phology image of PαMS film (10 µm × 10 µm) illustrates the surface root-mean-square roughness is 492 pm showing a very good surface roughness and pinhole-free features, which favor the growth of pentacene and provide good pentacene/PαMS interfacial properties. For the device based on 80 °C grown pentacene and 50 µm channel length (denoted as “T-80/L-50”), the typical memory characteristics are shown in Figure 1b–e (V_ds= −5 V). The threshold voltage (Vth) is defined as the gate voltage (V_gs) at which the drain current (I_ds) reaches 10 nA. In addition, V_th+ and V_th− represent the threshold voltages after positive (writing) and negative (erasing) processes, respectively, and ΔVth is the difference between V_th+ and V_th− that is defined as the memory window.

The memory and trapping behaviors exhibit two features as shown in Figures 1b,c and d,e, respectively. First, the device was subjected to programming (positive V_gs) and erasing (nega- tive V_gs) pulses (Figure 1b), which would induce majority (holes) and minority (electrons) carriers to be transported along and then trapped at the pentacene/PαMS interface. After the application of a negative pulse of −20 V/10 ms, the transfer curves significantly shifted toward negative with V_th− values of −16.2 V (Figure 1c), clearly indicating hole trapping in the PαMS layer. Subsequently, a positive pulse of +20 V/1 s was applied but the transfer curves showed no displacement, with similar V_th+ values of −16.1 V. The result shows the lack of minority (electrons) injection from the pentacene channel to PαMS, which would otherwise lead to positive shift as depicted by dashed arrows in Figure 1c. Such a memory behavior can be identified as WORM-type memory behavior.^[11,14] Second, the device was subjected to continuous transfer scanning and, in each cycle, the device was scanned from +40 V to −40 V and then back to +40 V. In Figure 1e, the transfer hysteresis gradu- ally shifted toward positive after continuous scanning cycles (2nd–16th). The results imply that electron trapping in the

Figure 1. a) Schematic diagram of the N⁺⁺Si/SiO₂/PαMS/pentacene/Cu PEM device. b) Schematic diagram of the ambipolar pulse test (+20 V/1 s and −20 V/10 ms). c) I_ds–V_gs curves (V_ds=−5 V) after a programming pulse (+20 V/1 s) and erasing pulse (−20 V/10 ms). d) Schematic diagram of continuous transfer scanning cycles of +40 V→ −40 V→ +40 V. e) Ids–Vgs hysteresis characteristics of the T-80/L-50 devices (Vds = −5 V).

pentacene channel or in the PαMS layer could occur but, in contrast to hole trapping, this process takes a much longer time scale to reach saturation or equilibrium.

To separate the impact of hole trapping and electron trap- ping in determining the memory window in a transfer scan- ning (Figure 1e), we compared negative and positive scanning and read V_th for several cycles, as shown in Figure 2. In each cycle, V_gs was first swept toward negative (0 V → −40 V → 0 V) or positive (0 V → +40 V → 0 V) at Vds = −5 V. Then, a reverse pulse was applied to verify whether carriers could be suffi- ciently injected and trapped after continuous voltage scans.

The V_th+ or V_th− values were read from the I_ds–V_gs curves after programming (+20 V/1 s) or erasing (−20 V/10 ms), as shown in the inset of Figure 2b. In negative cycles, both V_th+ and V_th− remained nearly unchanged at approximately

−16.88 and −18.92 V, respectively. The memory window is narrow even after 20 test cycles. In contrast, with positive cycles, V_th+ changed significantly and gradually shifted toward positive (Figure 2d). The resulting memory window is much wider (≈18 V) after 13 positive test cycles. The comparative studies clearly demonstrate that injection and accumulation of minority electrons rather than majority holes play a critical role in the unipolar WORM memory characteristics of the PEM device.

The PEM device exhibits single polarity, stable memory effect (Figure 1c) after short pulses and a gradually changed memory window after continuous transfer scanning (Figure 1e), whereas the ideal electret memory device should exhibit bistable memory effect and a stable memory window. Ambipolar memory devices with large memory windows can be applied in both multi-level memory and low-voltage operations.^[25,26] To

achieve ideal ambipolar, bistable, and fast memory, we study the critical factor affecting the memory, i.e., dynamic trapping of minority carriers, in the following sections.

2.2. Dynamic Process of Electron Trapping

The dynamic process of electron trapping with applying posi- tive V_gs was investigated in detail. The same pulse height (V_gs= +20 V) was applied with different time width (from 1 to 48 s) onto the above device. The I_ds–V_gs curves after each pro- gramming pulse are shown in Figure 3a. The shift threshold voltage (V_th+) indicating the number of trapped electrons is extracted as a function of time and depicted in Figure 3b. The I_ds at V_gs= 0 V (denoted as Ids,0) is also shown in Figure S2 (Supporting Information). The evolution of V_th+ and I_ds,0 indi- cates the trapping of minority carrier electrons could probably be divided into two stages, where the first stage consumes longer time and contributes to less electron trapping than the second stage does. To confirm such features of trapping and to compare different semiconducting films, we fabricated devices with pentacene film deposited at 100 °C (“T-100/L-50”), which exhibits larger grain sizes and less grain boundaries as com- pared with that deposited at 80 °C (“T-80/L-50”), as shown in Figure S3 (Supporting Information). The I_ds–V_gs curves are measured by using +17 V pulse height and different pulse width ranging from 1 to 8 s, as shown in Figure 3c. The evo- lution of V_th+ and I_ds,0 against time (Figure 3d and Figure S2, Supporting Information) exhibits the same trends but with a much shorter time scale to reach the saturation. The maximum of V_th+ is similar for the two devices, indicating that the total

Figure 2. a) Schematic diagram of the negative test cycles. b) V_th+ (V_th+ and V_th−) as a function of the number of negative cycle tests. The inset shows the I_ds–V_gs curves after a programming pulse (+20 V/1 s) or erasing pulse (−20 V/10 ms) to read the V_th+ and V_th− values. c) Schematic diagram of the positive test cycles. d) V_th+ and Vth− as functions of the number of positive cycle tests.

number of trapped electrons at equilibrium is determined by the same PαMS film rather than the bulk semiconductor.

To separately investigate the effect of vertical injection, we fabricated the MIS structure (N⁺⁺Si/SiO₂/PαMS/Pentacene/

Cu; Figure 4a) and characterized the capacitance–voltage (C–V) for charge trapping and memory behaviors. Carrier movement is limited to the vertical direction,^[27–29] i.e., from Cu into penta- cene, through the bulk pentacene, across the pentacene/PαMS interface, and finally trapped in the PαMS layer. Typical C–V characteristics for the device with pentacene films grown at 80, 100, and 120 °C are shown in Figure 4b and Figure S4 (Sup- porting Information). The excellent retention of the high and low capacitance suggests that the charges were deeply trapped in the PαMS layer but not in the shallow traps (Figure S5, Sup- porting Information). The memory windows, defined by the

difference in the flat-band voltage (V_fb), were all stabilized at the first cycle. As shown in Figure 4b, the flat-band voltage (V_fb) is determined by flat-band capacitance C_fb = (Cmax − Cmin) × 0.66 + Cmin.^[30] The width of memory window ΔVfb should be dependent on the total trapped charges and thus the starting voltages (V_st), i.e., Vfb Q Ct/ i _V^V(V t) A V( st V0)2

st

∑

0

∆ = ∝ ∆ = − . Here, Q_t

is the trapped charges, C_i is the capacitance per unit area, Δt is the time interval for each voltage, V₀ is the threshold value, and A is a constant. Such a relation well describes the experi- mental data (Figure 4c) and all the devices with pentacene films grown at different temperatures (i.e., with different grain sizes) exhibited nearly the same memory window (shown in Figure S4, Supporting Information), unlike the OTFT-based devices.

In contrast with that of the OTFT-based devices, the memory window of the MIS-structure devices is ambipolar, independent

Figure 4. a) Schematic diagram of the N⁺⁺Si/SiO₂/PαMS/pentacene/Cu capacitive memory device. b) High-frequency (1 MHz) C–V characteristics of N⁺⁺Si/SiO2/PαMS/pentacene/Cu capacitive memory devices with pentacene films grown at 80 °C under different sweeping voltages. c) Comparison of the memory window widths at different sweeping voltages for devices with pentacene deposited at different temperatures.

Figure 3. Ids–Vgs curves of PEM devices after a programming pulse with different time, where Vds = −5 V: a) T-80/L-50 PEM device (+20 V pulse height) and c) T-100/L-50 PEM device (+17 V pulse height). The Vth+–t data and fitting curves of different PEM devices: b) T-80/L-50 and d) T-100/L-50 PEM devices.

on grain sizes, and stabilized at the first cycle. Such results con- firm that lateral transport rather than vertical injection plays the critical role in determining the memory properties of OTFT- based devices.

2.3. Mechanisms and Models for Electron Trapping

To explore the origin for the memory in materials, the energy levels of the defect states in the PαMS and pentacene films were investigated by photoluminescence (PL) and photo- luminescence excitation (PLE) measurements on N⁺⁺Si/SiO₂/ PαMS samples and N⁺⁺Si/SiO₂/PαMS/Pentacene. For the N⁺⁺Si/SiO₂/PαMS samples, the PL spectra excited by 325 nm laser on the sample are shown in Figure 5a. As the PαMS film cannot withstand high temperatures, only small intensity of excitation laser can be applied to the sample surface. The emis- sion peaks at 2.74–3.04 eV and at 2.38–2.51 eV are not due to the band-to-band recombination from PαMS (6.7 eV) film^[31]

or SiO₂ (9.0 eV) film, but are most possibly due to the signifi- cant distribution of defects, which act as recombination centers within the bandgap in the PαMS films. By assuming most of the recombination is from the defect states to the highest occupied molecular orbital (HOMO) levels, we estimate that the gap states in PαMS films lie from 2.90 to 2.51 eV above the HOMO of PαMS.^[32] For the N⁺⁺Si/SiO₂/PαMS/Pentacene sample, the PL and PLE spectra are shown in Figure 5b and Figure S6 (Supporting Information), respectively. It exhibits the same peaks at 2.04−2.13 eV of PL spectra for pentacene films

grown at different temperatures. We estimate that the center energy levels of the traps lie between 2.04 and 2.13 eV above the HOMO of pentacene. By summarizing the PL spectra, a schematic diagram of the energy level positions of the trap states in PαMS and pentacene is depicted in Figure 5c.^[27,31]

Based on the above optical and electrical measurements, the mechanism is proposed to explain the electron trapping pro- cesses of WORM-type memory devices (Figure 5d,e). When erasing (negative V_gs) with a short pulse (1 ms), many holes available in the pentacene channel are injected and trapped in the pentacene/PαMS interface, inducing negative Vth− shift during the first voltage scan. Such a process is fast so that further applying negative V_gs does not lead to additional holes injected into the trap states due to column blockage effect. When pro- gramming (positive V_gs) with a single pulse, very few electrons available in the pentacene channel are trapped and thus V_th+ did not shift toward positive. This is attributed to the large electron injection barrier at the electrodes, the low electron mobility for transport (≈5.3 × 10⁻² cm² V⁻¹ s⁻¹),^[33] and the large amount of bulk electron traps (2.04 to 2.13 eV above the HOMO). With continuously applying positive V_gs, more electrons are injected and laterally transport along the channel and occupy the bulk trap states. Such a process is denoted as Process A and illus- trated in Figure 5d. After sufficiently filling the bulk trap states in pentacene, electrons are possible to be injected into the trap states in PαMS layer close to the pentacene/PαMS interface.

Besides, some electrons in the pentacene channel under the S/D electrode may be directly injected into the PαMS film to be trapped. Such a process related to vertical injection of electrons

Figure 5. a) Photoluminescence spectra of N⁺⁺Si/SiO2/PαMS sample (excitation wavelength is 325 nm). b) Photoluminescence spectra of N⁺⁺Si/SiO2/ PαMS/Pentacene sample (excitation wavelength is 400 nm). c) A schematic diagram of energy level positions of trap states in PαMS and pentacene and band alignments of the N⁺⁺Si/SiO₂/PαMS/Pentacene/Cu gate stack. Schematic diagrams of carrier transport during P/E processes: d) minority electron transport during voltage scanning cycle and e) hole trapping during voltage scanning cycle.

through the interface and into gap states in PαMS is denoted as Process B and illustrated in Figure 5e by yellow arrows. Both the processes lead to positive shift of I_ds–V_gs curves.

The above mechanism explains the electric characteristics shown from Figures 1 to 3. Due to abundant electron trap sites and slow lateral transport of electrons, a pulse of positive V_gs to inject electrons in 1 s is not enough to positively shift I_ds–V_gs curves (Figure 1c). For the same reason, the memory window is gradually opened after several cycles of scanning (Figures 1e and 2d). We derive the relation between the concentration of trapped electrons n_t (cm⁻²) and time t (s) for the two processes.

For Process A, where n_tA(t) electrons are trapped mainly in bulk pentacene, the value could be described by the stretched expo- nential model as confirmed in many OTFTs^[34]

1 exp /

tA tA A

n ( )t =n ( )∞ −

(

t τ

)

^α (1) Here, n(∞) is the value at the saturation or equilibrium state (cm⁻²), τA is the time constant (s), and α is the stretching para- meter. Then change of V_th or on-voltage V_on is in the similar form. For Process B, n_tB(t) electrons are trapped mainly in the PαMS film near the pentacene/PαMS interface. At time t, the differential change of n_tB(t) is determined by the electrons at the trapping states in pentacene n_tA(t) and the unoccupied trapping sites [n_tB(∞)−ntB(t)] in PαMS film. For the first-order approximation, it follows

d d

tB

tA tB tB

n t

t^{( )}=γn ( )t n

[

( )∞ −n ( )t

]

(2) Here, γ is the trapping probability (cm⁻² s⁻¹) and n_tB(∞) is the value at the equilibrium state (cm⁻²). As trap filling is a dis- persive process, the trapping probability γ should have a power- law time dependence, γ = γ00 t^{β − 1}, where β is related to the temperature.^[34]

Then, the total concentration of trapped electrons n_t(t) is the sum of n_tA(t) and n_tB(t). Notice that only when the value of n_tA(t) approaches n_tA(∞) does the value of ntB(t) start to significantly increase. Hence, the evolution of n_t(t) could be approximated as a piecewise function

n t n t t t

n t t t t

1 exp / , when

1 exp / , when

t

tA A 0

tB 0 B 0

τ

{ ^{[ ( ( ) )}

τ

^] }

( ) ( )

≅ ( )∞  −  ≤

∞ − − >







α

β (3)

The resulting shift of V_th is then given by

V t qn t C

V t t t

V t t t t

1 exp / , when 1 exp / , when

th t

i

A A 0

B 0 B 0

τ

{ ^{[ ( ( ) )}

τ

^] }

( ) ( ) ( )

∆ = ≅ ∆ ( )∞  −  ≤

∆ ∞ − − >







α β

(4) Here, C_i is the capacitance per unit area, q is the elementary electric charge, and ΔVA(∞) and ΔVB(∞) are the constants that would decrease with decreasing the defect states in bulk pen- tacene and in PαMS film, respectively. Also, τA and τB are the time constants that would decrease with increasing the lateral transport mobility and vertical injection probability. A slow Pro- cess A would also lead to a slow Process B, mainly by elongating the time to fill the emptied trap states in bulk pentacene during injecting electrons into PαMS film. Equation (3) well describes the data in Figure 3b,d (curves) with the fitting parameters list in Table S1 (Supporting Information). Processes A and B are mainly dominant in stages 1 and 2 shown in Figure 3, respec- tively. In particular, the fitting results are good when setting the parameter β as 1, indicating that trapping probability in Process B is nearly time independent in the current system. Also, with the same time parameters, evolution of I_ds at V_gs= 0 V is well fitted by the similar equations (Figure S2, Supporting Informa- tion), again validating the above model.

2.4. Controlling Lateral Transport to Achieve Ambipolar, Bistable Memory

The above mechanisms and models indicate that controlling the lateral transport would efficiently control the memory effect. We investigated the devices with different grain sizes or with different channel length. Different grain sizes were obtained by varying the substrate temperature when depositing pentacene (80, 100, and 120 °C) and the surface morphologies and grain sizes obtained by AFM are shown in Figure S3 (Sup- porting Information). All the devices were scanned by the same programming (+20 V/1 s) and erasing (−20 V/10 ms) cycles and the charge trapping density nt=^{C Vi∆}_q^th and trapping rate ^dn_dt^t are calculated. First, when comparing devices with different grain sizes (Figure 6a and Figure S7, Supporting Information), the devices with larger grain sizes (100 °C) reach saturation only after one cycle with a fast trapping rate, while the memory

Figure 6. Typical Ids–Vgs curves to calculate the trapped charge density and charge trapping rate of PEM devices after a programming pulse (+20 V/1 s). Electron trapping density and charge trapping rate for devices a) with different grain size of pentacene and b) with different channel lengths.

window of the devices with smaller grain sizes (80 and 120 °C) is gradually open after several cycles. This is because larger grain sizes lead to lower trap densities and faster transport in the channels.^[35–37] Second, when comparing devices with dif- ferent L (Figure 6b and Figure S8, Supporting Information), the longer channel devices (L = 200 or 350 µm) need more transfer cycles to fully open the memory window as compared with the shorter one (L = 50 µm). This can be explained by that a longer distance and reduced lateral electric field would lead to longer time for electrons to hop and fill traps, i.e., with a slower trapping rate. The results are highly consistent with the above model and indicate the importance of highly ordered semicon- ductor films and short channel length in fast formation of sta- bilized, ambipolar OTFT-based memory devices.

The optimized device (“T-100/L-50”) exhibits bistable cur- rent states after P/E processes (Figure 7a). Also, in the transfer hysteresis with a voltage scanning cycle of +40 V → −40 V

→ +40 V, a large memory window of about 24 V and an ON/

OFF ratio larger than 10⁵ at V_gs = 0 V and Vds = −5 V were obtained after the first cycle scanning (Figure 7b). This is in sharp contrast with the unipolar, WORM-type memory and gradually enlarged memory window shown in Figure 1. Due to the injection of both holes and electrons into PαMS, bipolar storage characteristics have been achieved.^[10,19] The difference in P/E pulse width shown in Figure 7a is attributed to that the concentration of holes in pentacene was higher than that of electrons.^[38] Figure 7c illustrates the retention characteristics of the OTFT memory in both the ON and OFF states, where the ON/OFF ratio remained higher than 10⁵ after 3 h. Based

on extrapolation, this corresponds to a ratio of 5.5 × 10⁴ after 10 years and demonstrates the excellent retention characteris- tics. Figure 7d shows the endurance properties and the device showed a stable memory window compared to the initial state even after 5000 P/E cycles. To the best of our knowledge, the proposed device exhibits the best endurance properties among polymer electret-type OTFT memory devices by using SiO₂ as dielectric (shown in Table 1).^[19,39–55]

3. Conclusion

Device physics of OTFT-based polymer-electret memory devices has been investigated. The unipolar memory behav- iors after short pulse and gradually enlarged memory window after continuous scanning are revealed to be the result of poor lateral transport of minority carriers (electrons) in organic semiconductors. The slow electron-trapping process has been well explained by a two-stage model that takes both the bulk and interfacial traps into account. By using less disordered semiconducting film and short channel length, lateral trans- port and trapping of minority carriers (electrons) is optimized and, thus, ambipolar, bistable memory behaviors have been obtained. This is in sharp contrast with the initial unipolar, WORM-type memory and well illustrates the importance of the lateral transport and trapping of minority. These insights are expected to contribute to the understanding, designing, and fabrication of high-performance organic, nonvolatile memory devices.

Figure 7. a) I_ds–V_gs curves after a programming pulse (+20 V/1 s) or erasing pulse (−20 V/10 ms). b) Ids–V_gs hysteresis characteristics of the OTFT memory devices (V_gs was swept between +40 V and −40 V at V_ds of −5 V). c) Retention characteristics (read at V_gs= 0 V and V_gs=−5 V) after a pro- gramming pulse of +20 V/1 s or an erasing pulse of −20 V/10 ms. d) Endurance properties during repeated P/E pulses of +20 V 1 s and −20 V/10 ms.

4. Experimental Section

Fabrication of OTFT and MIS Memory Devices: Memory devices based on OTFT and MIS structures were fabricated according to the schematic diagram of the PEM device shown in Figure 1a. Heavily doped Si (100) and 50 nm thick SiO2 were employed as the back-gate electrode and blocking insulator, respectively. After cleaning of the wafers, the Si substrates covered with 50 nm thick layer of SiO₂ were exposed to UV–O₃ radiation for 5 min. The SiO₂ surface after 5 min UV–O3 irradiation time showed not only a good surface wettability but also a clean surface. Subsequently, PαMS dissolved in toluene was spin-coated on top of the SiO₂ layers followed by drying at 120 °C for 15 min on a hot plate. Subsequently, a 40 nm thick pentacene film was deposited by thermal vacuum evaporation (pressure = 4 × 10⁻⁴ Pa, growth rate = 0.5 Å s⁻¹) at different substrate temperatures (80, 100, and 120 °C). Finally, copper (Cu) electrodes were evaporated through a shadow mask to form the MIS and OTFT memory devices. The OTFT memory devices had channel lengths ranging from 50 to 350 µm and the same channel width of 750 µm. For the MIS memory devices, pentacene and Cu top electrodes with sizes of 3.14 × 10⁻⁴ cm² were deposited on the PαMS surface using the same dot-shaped shadow mask.

Characterization of Microstructure and Electrical Properties: The surface morphologies of the pentacene and PαMS films were characterized by AFM (Asylum Research) in tapping mode. Figure S1 (Supporting Information) shows a typical AFM image (10 µm × 10 µm) of the PαMS film. The average grain sizes of the organic semiconductor pentacene grown at different substrate temperatures were estimated using image processing software (Image-Pro Plus). The fluorescence spectra were estimated using computer-controlled F-4600 fluorescence

spectrophotometer (HITACHI, Japan) for analysis. The memory characteristics of the PEM devices were evaluated using a high-precision semiconductor device analyzer (Agilent B1500A). The capacitance–

voltage (C–V) characteristics of the MIS memory devices were measured using an LCR meter (Agilent E4980A). All electrical measurements were performed in the dark under high vacuum (<5 × 10⁻³ Pa) in a Janis temperature variable probe station.

Supporting Information

Supporting Information is available from the Wiley Online Library or from the author.

Acknowledgements

This work was supported by the National Natural Science Foundation of China (Contract No. 51872099). X.B.L. acknowledges the support of the Project for Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme (2016). C.L. acknowledges the financial support of the project from the Guangdong Provincial Department of Science and Technology (2019B010924002) and the Guangdong Natural Science Funds for Distinguished Young Scholars under Grant 2016A030306046.

This work was also supported by the Guangdong Innovative Research Team Program (Grant No. 2013C102), the Guangdong Provincial Key Laboratory of Optical Information Materials and Technology (Grant No.

2017B030301007), and the 111 Project.

Table 1. Comparison of polymer electret-type OTFT memory devices by using SiO2 as dielectric.

Device architecture Operation

voltage [V]

Operation speed [s]

Memory ratio

Retention time [s]

Endurance [cycles]

Year Ref.

n⁺⁺Si/SiO2/PαMS/Pentacene/Cu +20/−20 1/10⁻² 10⁵ 10⁴ 5 × 10³ This work

n⁺⁺Si/SiO2/PαMS/Pentacene/Au +200/−100 10⁻⁶ 10⁵ 3 × 10⁴ 10² 2006 [39]

n⁺⁺Si/SiO2/PαMS/Pentacene/Au ±20 1.5 × 10⁻³ 10⁴ 10⁷ – 2009 [19]

n⁺Si/SiO2/MH(4Py-Acceptor-4Py)x-b-PPyMAn/

Pentacene/Au

±50 2 10⁶ 10⁴ 10² 2016 [40]

n⁺Si/SiO2/CuPc-PS4/Pentacene/Au ±50 1 10⁷ 10⁴ 10² 2016 [41]

n⁺Si/SiO2/P3HT44-b-Pison/Au ±100 1 10⁴ 10⁴ 10² 2016 [42]

n⁺⁺Si/SiO2/C NPS/PS/Pentacene/Cu ±80 1 10⁵ 10⁴ 10³ 2014 [43]

Si/SiO2/PPF/Pentacene/Au ±120 1 10⁵ 10⁴ 10³ 2014 [44]

n⁺Si/SiO2/PI(6FOH-ODPA) blended with 15%

AM4/Pentacene/Au

±40 1 10³ 10⁴ 10² 2016 [45]

n⁺⁺Si/SiO2/Li⁺@C60/Cytop/Pentacene/Cu ±150 5 × 10⁻¹ 10¹ 5 × 10³ – 2017 [46]

n⁺⁺Si/SiO2/PS-brush/N2200:TIPS-PEN blend(6:1)/Au

+100/−120 1 10⁷ 10⁴ 10² 2019 [47]

n⁺⁺Si/SiO2/D-A Particles/Pentacene/Au ±50 1 10⁴ 10⁴ 10² 2019 [48]

Si⁺⁺/SiO2/New polymers P1/Pentacene/Au ±120 10¹ 10⁶ 10⁴ 10² 2019 [49]

n⁺⁺Si/SiO2/PVP/Pentacene/P13/Pentacene/Au ±120 1 10⁵ 10⁴ 3 × 10³ 2017 [50]

n⁺⁺Si/SiO2/PyPN/Pentacene/Au Light/−80 1 10² 10⁴ 1.5 × 10² 2018 [51]

n⁺⁺Si/SiO2/TMP/WG3/Pentacene/Cu Light/−100 1 10⁴ 10⁴ 1.5 × 10² 2018 [52]

n⁺⁺Si/SiO2/CuSP1/Pentacene/Au +100/−100 5/1 10⁵ 10⁴ – 2018 [53]

n⁺⁺Si/SiO2/TPA-PES/Pentacene/Au ±150 15 10² 10⁴ 10² 2018 [54]

n⁺⁺Si/SiO2/TPA(PDAF)3/Pentacene/Au +100(Light)/−100 1/2 × 10⁻² 10⁴ 10⁴ 10² 2018 [55]

Conflict of Interest

The authors declare no conflict of interest.

Keywords

charge trapping, lateral charge transport, minority carrier, polymer electret memory, write-once-read-many memory

Received: November 27, 2019 Revised: January 17, 2020 Published online: February 25, 2020

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