Creating a simple datapath: ALU control lw, sw beq

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A Simplified MIPS Implementation

Full credit of these slides is given to Dr. Mohammad Sinky 1

Computer Architecture – 2316315 Umm Al-Qura University

1439H (2018G)

Dr. Abdulbasit Abid

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• Computer architecture =

Instruction set architecture + Computer organization

• Instruction set architecture (Chapter 2)

• Language of the computer

• Instruction consists of opcode and operands

• Opcodes are the actual operations

• Operands are data on which operations are performed

• Computer organization (Chapter 4)

• How to implement instruction set architecture

• How instructions are executed

Review

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• Why we study computer architecture ?

• To increase computer performance

• What is computer performance ?

• Execution Time (latency)

• Time taken by a single instruction

• Bandwidth (Throughput)

• Number of instructions executed per unit time

• Performance factors

• Instruction count: Determined by ISA and compiler

• CPI & Clock Cycle time: Determined by implementation of the processor

Review

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CPU

A typical CPU has three major components:

(1) Register Set:

• the program counter (PC): used to hold the address of the instruction to be executed next

• the instruction register (IR): used to hold the instruction that is currently executed

(2) Arithmetic Logic Unit (ALU):

• provides the circuitry needed to perform the arithmetic and logical operations

(3) Control Unit (CU):

• responsible for fetching the instruction to be executed from the main memory, decoding and then executing it

D at ap at h C o n tr o l

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Building a MIPS implementation

• Simplified Implementation will only have

• Memory-reference instructions: lw, sw

• Arithmetic-logical instructions add , sub , AND , OR and slt

• Branch equal ( beq ) and jump ( j )

• the choice of various implementation strategies affects clock rate and CPI

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Instruction Execution Process

• Regardless of the instruction class (arithmetic, logic, memory, branches) the first two steps of instruction execution process are the same:

• Step 1: send PC to memory to fetch instruction

• Step 2: Decode instruction and read registers

• Step 3: Instruction execution depends on actual instruction

Use ALU to do

Arithmetic result

Memory address calculations for load/store

Branch comparisons

Access data memory for load/store

PC  target address (for branch instruction) or PC + 4 (for next instruction)

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Digital Logic Design

• We need to know how the hardware logic operate and how the computer is clocked

• Datapath elements in MIPS:

1. Combinational elements: operate on data values i.e. output depends on current input (AND gates, ALU) (no internal storage)

2. Sequential or state elements : memory element (ex. registers, memory) has

• at least two inputs

• data to be written into the element

• clock determines when state element is written

• one output (value written in earlier clock)

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Clocking methodology

• Clocking methodology: Defines when data can be read and when they can be written

State element

1

State element

2

Combinational logic

edge-triggered (positive) All signals must propagate from state element 1, through combinational

logic, and to state element 2 in the time of one clock cycle

An edge-triggered methodology allows us to read the contents of a register, send the

value through some combinational logic, and write that register in the same clock cycle

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Sequential Elements

• Register: stores data in a circuit

• Uses a clock signal to determine when to update the stored value

• Edge-triggered: update when Clk changes from 0 to 1

D Clk

Q

Clk

D

Q

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Sequential Elements

• Register with write control

• Only updates on clock edge when write control input is 1

• Used when stored value is required later

D Clk

Q Write

Write

D

Q

Clk

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Datapath:

• Elements that process data and addresses in the CPU

 Registers, ALUs, mux’s, memories, …

• We will build a MIPS datapath incrementally

Building a Datapath

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Building a Datapath

(Major components required to execute each class of MIPS instructions)

• (Instruction memory)

• Need a memory unit to store instructions of a program

• Simple implementation

• Only need address to access instruction

• No write signal

• Program Counter (PC)

• Register that holds the address of the current instruction

• Recall that each instruction is 32-bits wide

• Adder to increment PC by 4

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Building a Datapath

• (Register File) see Appendix B, B-54

• Is a collection of registers

• Any reg. can be read or written by specifying reg. #

• To read: supply a reg. # (No control signal needed)

• To write: we need four inputs

1. Reg. #

2. Data to write

3. Write control signal and Clock

• (ALU) see Appendix B, B-26

• To operate on the values read from the reg. (Add, Sub, AND, OR)

• Constructed from AND, OR, INVERTER, MULTIPLEXER

• Takes two 32-bit inputs

• Produces:

• a 32-bit result

• 1-bit signal if the result is 0 ( for branches)

• 4-bit control signal

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Building a Datapath

• (Data Memory)

• Two inputs: address and write data

• One output: read result

• Controls: MemRead and MemWrite

• (Sign Extension Unit)

• Inputs: 16-bit

• Output: 32-bit result

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Building a Datapath: Fetch

• For execution recall the first step is to Fetch instruction from memory

• PC points to location of instruction

• To prepare for executing next instruction, increment PC: PC  PC + 4

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Building a Datapath: Execute

• How to execute the following instructions?

1. Artihmetic-logical instructions add, sub, AND, OR and slt 2. Branch equal (beq) and jump (j)

3. Load word (lw) and store word (sw)

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• Start with R-format instructions ( add , sub , AND , OR,NOR , slt) which require:

1. Reading two registers

2. Perform an ALU operation on contents of registers 3. Write the result to register

• So we need:

1. Register File: to read and write from and to registers

2. ALU : to operate on the values read from the reg.

Building a Datapath: (R-format)

Ex. add $t0, $s1, $s2

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Building a Datapath:

(1) Register file read & write ports implementations (Appendix B)

op rs rt rd shamt funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

For data word to be read from reg. we need:

• input to reg. file with reg.

# to be read

• output from reg. file carrying that reg. data

To write a data word to reg. file we need:

• two inputs one with reg. # to be

written and one to supply data

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Building a Datapath:

(2) ALU (Components)

• For ALU component

• Inputs: ALU operation (4 bits) and two operands (each 32 bits)

• Outputs: ALU result (32 bits) and zero (1 bit)

• We want to be able to perform add , sub , AND , OR,NOR , slt

• Start with 1-bit ALU and build

• Logic – AND , OR

• Arithmetic – include Full Adder

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Building a Datapath: ALU(AND, OR, Add)

32-bit: Repeat and connect CarryOut to CarryIn 32 ALUs

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Building a Datapath: ALU(Sub, NOR)

�� : � − �= �+ ( − � ) =� +� + 1 �� : ( � + � ) =� ∙ �

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Building a Datapath: ALU(slt)

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Building a Datapath: ALU(Branch)

• Branch operations:

• So if the result is 0 we can test for equality

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Building a Datapath: ALU (Operation)

ALU operation Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 Set on less than

1100 NOR

• ALU control

• Ainvert (1 bit)

• Binvert (1 bit)

• Operation (2 bits)

4-bit control lines

for the ALU

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Building a Datapath: (R-format)

• Fetch

• R-format ( AND , OR , add , sub , slt , NOR ) ready to build

op

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Building a Datapath: lw and sw

• Recall lw and sw

• lw $t1, offset_value($t2)

• sw $t1, offset_value($t2)

(Need: Register file, ALU and Sign Extend Unit)

• Both instructions compute memory address offset_value + $t2

offset_value : 16-bit signed value

(Need data memory) Load: writes to $t1

Store: reads from $t1

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• beq $t1, $t2, offset

• Branch Target Address: (PC + 4)+4(offset)

• Compares between contents of $t1 and $t2

•

Building a Datapath: beq

Need:

• Sign Extend

• Adder

• PC

• Register file

• ALU

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Creating a simple datapath

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Creating a simple datapath: (components)

Fetch

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Creating a simple datapath: (components)

R-type

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Memory

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Branches

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Creating a simple datapath: Control Unit

Control Unit

Op-Code

Instruction field [31-26]

Read and Write signals

MemRead MemWrite RegWrite

Mux selector:

RegDst Branch MemtoReg ALUSrc

ALU Control: ALUOp Input

Output

Control signals

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Creating a simple datapath: ALU control

ALU operation Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 Set on less than

1100 NOR

Depending on instruction class ALU will do one of those functions:

• For lw and sw ALU compute: memory address by addition

• For R-type ALU perform one of these: AND, OR, sub, add, slt (depending on func field)

• For beq ALU perform: subtraction Generating 4-bit ALU lines:

• 6-bit func field

• 2-bit ALUOp (designed & come from the cont. unit)

• add (00) for load and store (Mem. Inst.)

• subtract (01) for beq (Branch Inst.)

• One of Operations in func field (10) (R-type Inst.)

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Creating a simple datapath: ALU control

lw, sw beq

R -t yp e

By logic minimization program

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• The op field,, is always contained in bits 31:26.

• The two registers to be read are always specified by the rs and rt fields, at positions 25:21 and 20:16. This is true for the R-type instructions, branch equal, and store.

• The base register for load and store instructions is always in bit positions 25:21 (rs).

• The 16-bit offset for branch equal, load, and store is always in positions 15:0.

• The destination register is in one of two places. For a load it is in bit

positions 20:16 (rt), while for an R-type instruction it is in bit positions 15:11 (rd). Thus, we will need to add a multiplexor to select which field of the

instruction is used to indicate the register number to be written.

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9 control signals 1. RegDst

2. RegWrite 3. ALUSrc 4. PCsrc 5. MemRead 6. MemWrite 7. MemtoReg 8. ALUOp (2 bits)

All signals depend on the opcode field (bits 31:26 of instruction)

mux needed

mux needed mux needed

mux needed

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Complete Datapath with Control Signals

2. RegWrite 3. ALUSrc

4. (Branch) PCsrc 5. MemWrite 6. MemRead 7. MemtoReg 8. ALUOp (2 bits)

All signals depend on the opcode field (bits 31:26 of instruction)

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Control Signal Activation: (R-type)

ALUOp1=1

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Control Signal Activation: (load)

4. (Branch) PCsrc

5. MemWrite

6. MemRead

7. MemtoReg

8. ALUOp (2 bits)

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Control Signal Activation: (beq)

ALUOp0=1

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Designing Control: Main Control

• Depending on Instruction type, certain signals must be asserted/deasserted.

• R-format: opcode = 000000

• lw: opcode = 100011

• sw: opcode = 101011

• beq: opcode = 000100

Control signals will be designed based on these values

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Designing Control: Truth Table for Main Control

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How to add jump instruction?

• Recall J-format instructions

• Jump replaces PC + 4

address

00

PC + 4

[31:28]

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Datapath and Control including Jump

4. (Branch) PCsrc

5. MemWrite

6. MemRead

7. MemtoReg

8. ALUOp (2 bits)

9. Jump

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Example: Addition

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Ex. add $t1, $t2, $t3

everything occurs in one clock cycle 1. Instruction Fetched:

• op=000000 (R-type), func = 10000 (add),

rs [25-21] =01010 ($t2), rt [20-16] = 01011 ($t3) rd [15-11] = 01001

• ALUOp1=1 (i.e. R-type)

• ALU operation 0010 (i.e. add)

• RegDst = 1 (i.e. code of destination register comes from inst. field [15-11] which is rd field

• RegWrite = 1 (write result to dest. reg.)

• MemtoReg = 0 (not lw)

• ALUSrc = 0 (not lw or sw) 2. PC incr. (Branch and Zero are 0’s) 3. Reading registers from register file

4. ALU perform addition(ALUOp1=1, ALU operation 0010 ) 5. Result is written into register file (RegWrite = 1)

ALU operation Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 Set on less than

1100 NOR

01010 01011 01100 0 100000

000000

Example: Addition

$s0 – $s7 : registers 16 – 23

$t0 – $t7 : registers 8 – 15

$t8 – $t9 : registers 24-25